PLL and retaining frequency

Discussion in 'General Electronics Chat' started by kubeek, Aug 19, 2012.

  1. kubeek

    Thread Starter AAC Fanatic!

    Sep 20, 2005
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    I have a stream of amplitude modulated data coming over a 13,56mhz carrier. Because the transmitter is powered for short times, I need to synchronize the reciever´s clock to this carrier and keep running when the transmitter is turned of for some short time.

    I was thinking I could use a PLL for this, but I never used it so I am open to suggestions ;)
     
  2. crutschow

    Expert

    Mar 14, 2008
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    You could possibly use a PLL with a long feedback loop time constant so the frequency doesn't change much when the input signal is removed or perhaps inhibit any output change of the PLL phase-detector when no signal is detected.

    How long is a "short time"?
     
  3. kubeek

    Thread Starter AAC Fanatic!

    Sep 20, 2005
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    To be honest, my ultimate goal is to make a proximity card accroding to iso/iec 14443, at least mode A, where the bit frequency 106kbps and the data is modulated using 100% ASK modulation.
    Now that I think of it I am not really sure if I need to use a frequency- or phased-locked loop to demodulate that. I think that if I can sample some envelope detection at 4-16x rate I should be ok.

    I will be using a microprocessor and the current budget is only around 3mA, so I quess what I actually need is some way to demodulate the ASK without a lot of active components. Maybe I could use the MPU´s comaprator and save an external, or even the ADC..

    I guess I will need to get some samples and try to see what kind of current the chip (msp430) consumes and how high clock frequency do I need to leave enough time for the useful stuff.
     
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