PLL 565 CLOCK RECOVERY (bit sync.)

Discussion in 'General Electronics Chat' started by vinodquilon, Mar 19, 2010.

  1. vinodquilon

    Thread Starter Member

    Dec 24, 2009
    234
    0
    I am using PLL for clock recovery (see attachment).
    http://www.scribd.com/doc/28612924

    What are the design criterion s for R1,C1,R2, and C4 ?
    R2 and C4 determines free-running frequency of PLL.

    What would be the selection for c2, which determines capture range ?
    Does there any restriction on VCC selection as it affects lock range ?

    Here I am using XOR to ensure frequent data transitions. That is to avoid Consecutive
    Identical Digit (CID).

    I am using this circuit in wireless communication to recover clock from received data for
    bit synchronization.
     
  2. vinodquilon

    Thread Starter Member

    Dec 24, 2009
    234
    0
    I think R1 & C1 should design to provide one bit delay time.
    R2 & C4 (VCO reference clock) should be tuned to lock at transmitter data rate.
    I am choosing C2= 10uF, VCC= 5V.
     
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