Please help me :-(

Discussion in 'Homework Help' started by Abanah, Jan 16, 2013.

  1. Abanah

    Thread Starter New Member

    Jan 16, 2013
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    Can u please post the verilog code for serial adder using fsm.. is it possible to write code for full adder using fsm..
    My project is based on fault tolerant system design in FPGA where i have to write codings for Duplex and TMR architecture. Can u please help me how to write codings in verilog for those architectures. Thanks in advance..

     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    This sounds like it's for a school project.

    So, show us what you've done. Show us the flow chart you made in order to understand what you need to do. Then we will help you write it.
     
    DerStrom8 likes this.
  3. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Please post an image of your state machine which you would like to be realized in Verilog.

    It's impossible to write code for a state machine that, from our point of view, does not exist.
     
  4. Abanah

    Thread Starter New Member

    Jan 16, 2013
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    I have attached the architecture for your reference. Fault tolerant architectures.jpg I have to write verilog coding for fault tolerant architectures based on finite state machine. The functional unit is considered as full adder. Functional unit (FU) together with that checker acts as FSM. Need help as how to proceed and write codings for those architectures. Thanks in advance.. Fault tolerant architectures.jpg
     
  5. MrChips

    Moderator

    Oct 2, 2009
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    I stop helping anyone who cannot post a proper title.
     
  6. tshuck

    Well-Known Member

    Oct 18, 2012
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  7. Abanah

    Thread Starter New Member

    Jan 16, 2013
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    I have attached the flow chart based on Fault tolerant design. contol flow of repair process.jpg
     
  8. WBahn

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    Mar 31, 2012
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    It sure is tempting -- I'm not quite there yet, but getting close!
     
  9. WBahn

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    Mar 31, 2012
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  10. Abanah

    Thread Starter New Member

    Jan 16, 2013
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    In DUPLchck architecture, I have constructed a full adder using fsm which signifies the functional unit(FU) along with the checker. Two functional unit blocks are taken in which error is introduced in one functional unit,i.e. full adder. Both the outputs of FU are given as input to the multiplexer. MUX gives output if any one of FU is operating correctly. If there is an error it generates error output.
    Full adder using FSM:
    module fsm(cin,clk,s);
    input cin,clk;
    output reg s,cout;
    reg [1:0]q;
    initial
    q=0;
    always @(posedge clk)
    begin
    q[1]<=q[1]^q[0]^cin;
    q[0]<=(q[1]&q[0])|(q[1]&cin)|(q[0]&cin);
    s<=q[1];cout=q[0];
    end
    endmodule

    In DUPLchckcmp , how the checker2 can be implemented.
     
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