Pipelining and Modified Datapath

Discussion in 'Homework Help' started by fred9527, Aug 11, 2015.

  1. fred9527

    Thread Starter New Member

    Aug 11, 2015
    2
    0
    Hi.
    I encountered this question today, and saw the answer too. I just have no idea why the circuit should be pipelined like this.
    My own attempts: I know pipelining is a technique that inserts registers between components so that it shortens the path that delays the most. So in this question, shouldn't registers be inserted whenever there is an adder? I cannot continue any further.
    Please kindly gimme some guidance on how to think when pipelining is required. Thank you in advance.

    Here is the question:
    1.png






    And here is the answer
    2.png
     
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