Piezo Transducer JFET Buffer

Discussion in 'The Projects Forum' started by EMFELAB, Aug 12, 2013.

  1. EMFELAB

    Thread Starter New Member

    Feb 11, 2013
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    I need to interface a Piezoelectric transducer sensor which will pick up frequencies up to 1000Hz. It was advised to me to use a JFET source follower circuit. The piezo transducer is simulated here as a AC source in series with a capacitor (10nF), as I understand the Piezo needs a very high input impedance so I haven't connected a RG across the input of the JFET since that would effectively bring down the input impedance of the circuit.

    When simulating this circuit, the output gives me 0V and I assume that the biasing is not right; placing a resistor across the gate brings down the signal to 0V DC but the output is still 0V. Now, if I get rid of C3 and R2 and I measure from the source, I get a signal with lower amplitude than the input and with a DC offset. Any suggestions??

    [​IMG]
     
  2. Ramussons

    Active Member

    May 3, 2013
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    We are all blinded without a schematic.

    Ramesh
     
  3. EMFELAB

    Thread Starter New Member

    Feb 11, 2013
    10
    0
    My bad. Here it is:

    [​IMG]
     
  4. MrChips

    Moderator

    Oct 2, 2009
    12,432
    3,360
    Change your circuit design to a common source circuit.
    You will need three resistors, one for the drain, source, and gate.
     
  5. MrChips

    Moderator

    Oct 2, 2009
    12,432
    3,360
    Note that your PN4392 is an N-channel depletion mode FET.
    There are four combinations, P-channel vs N-channel and depletion mode vs enhancement mode.

    For depletion mode, you need to bias the gate -ve with respect to the source in order to pinch off the channel. You do this with a resistor from the source to ground. You can add a 10MΩ resistor from the gate to ground to give the gate a reference voltage of 0V.
     
  6. DickCappels

    Moderator

    Aug 21, 2008
    2,650
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    If you just want an approximately unity-gain buffer, the circuit you already have should work fine, EXCEPT...you need to put a 1 meg to 10 meg resistor from the gate to ground so that the source voltage and be used to provide negative feedback to establish the FET's operation point.
     
    Last edited: Aug 12, 2013
  7. EMFELAB

    Thread Starter New Member

    Feb 11, 2013
    10
    0
    Mr Chip. I do not want a common source configuration, a source follower will do as I need a very high impedance. The simulation will not work if I do not bias the gate properly and this means having a gate resistor in parallel.

    At the beginning I did not want to do it since it would mean having a resistor parallel to the very high input resistance of the JFET and so lowering it. Therefore, as I understand, the input impedance is simply RG.
     
  8. #12

    Expert

    Nov 30, 2010
    16,261
    6,770
    There are ways to modify that input impedance. Look at this circuit.
     
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