PIC24H Interrupt Latency Diagram Help

Discussion in 'Embedded Systems and Microcontrollers' started by blah2222, Mar 5, 2012.

  1. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
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    Hey, I am starting to learn about interrupts and how they are executed and I ran into a little bit of confusion based on the reference manual by my textbook which is the same as the one written by Microchip.

    Interrupt Latency for One-Cycle Instruction

    [​IMG]

    This is straight from that manual:

    "Figure 29-3 shows the sequence of events when a peripheral interrupt is asserted during a one-cycle instruction. The interrupt process takes four instruction cycles. Each cycle is numbered in Figure 29-3 for reference.

    (1) The interrupt flag status bit is set during the instruction cycle after the peripheral interrupt occurs.

    (2) The current instruction completes during this instruction cycle.

    (3) In the second instruction cycle after the interrupt event, the contents of the Program Counter (PC) and Lower-Byte Status (SRL) registers are saved into a temporary buffer register.

    (4) The second cycle of the interrupt process is executed as a NOP instruction to maintain consistency with the sequence taken during a two-cycle instruction (see 29.3.2 “Interrupt Latency for Two-Cycle Instructions”).

    (5) In the third cycle, the PC is loaded with the vector table address for the interrupt source and the starting address of the ISR is fetched. In the fourth cycle, the PC is loaded with the ISR address. The fourth cycle is executed as a NOP instruction, while the first instruction in the ISR is fetched
    "

    ------------------------------------------------------------------------------------------

    Which current instruction is last executed INST(PC-2) or INST(PC), that the manual refers to in (2)? Also, what value for the PC is being stored as the return address? PC or PC+2?

    I am confused only because in the next section they describe the return process back to main code and the wording becomes tricky. I'm not sure which instruction address they return to. In the diagram it shows that PC = PC but is this the PC or PC+2 from the previous image?


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    "To return from an interrupt, the program must call the RETFIE instruction.

    During the first two cycles of a RETFIE instruction, the contents of the PC and the SRL register are popped from the stack.

    The third instruction cycle is used to fetch the instruction addressed by the updated program counter. This cycle executes as a NOP instruction.

    On the fourth cycle, program execution resumes at the point where the interrupt occurred.
    "

    I feel like they could have been clearer here.

    If anyone could help me out that'd be great! Thanks.
     
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    I think the confusion results from "PC" meaning both the current instruction (or reference point) and it also means the program counter register itself.

    What the micro does is save the address of the next instruction to be performed after the last non-interrupted executes.

    All processors do that, it is the only way things make sense. Each and every instruction is executed in turn, with the exception that the ISR code may be inserted between any two instructions.
     
  3. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    554
    33
    Okay this makes more sense, but just for me to solidify what I think is going on:

    An interrupt event occurs during the cycle of a certain (one-cycle long) instruction. This instruction is first completed and then the next (one-cycle long) instruction is completed. The PC then points to the next instruction address (third instruction in this case) but does not execute it. That address is then stored and returned to, once the ISR is finished.

    Does that sound right? Also, where are the addresses 2000, 2002, 2004, ... coming from? Are those specific areas that ISRs are defined in program memory?


    [​IMG]

    I'm also confused where data memory starts and program memory ends.
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    They are only using address 2000 as an example, with the assumption that the ISR is stored beginning at address 2000. This address is arbitrary and will be determined by the compiler and loader.
     
  5. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    554
    33
    I see.

    Does my interpretation sound correct?
     
  6. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    An interrupt event THAT occurs during the FIRST HALF OF THE cycle triggers off an interrupt event that starts at the end of the next instruction.

    An interrupt event THAT occurs during the LATTER HALF OF THE cycle triggers off an interrupt event that starts at the end of the next instruction PLUS ONE.

    (per the note bottom left corner of your very first diagram.)
     
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