PIC18F4550 configuration bit settings

Discussion in 'Embedded Systems and Microcontrollers' started by Vindhyachal Takniki, Apr 29, 2016.

  1. Vindhyachal Takniki

    Thread Starter Member

    Nov 3, 2014
    349
    6
    I am using PIC18F4550 with MPBALX IDE V2.26, Xc8 V1.32.
    I have connected external 8Mhz crystal with 22pF load capacitors.
    Below are configuration setting. I want system freq to run at 48Mhz & system clock also goes to USB
    Are these settings ok?
    Also code protection is on, so that code cannot be read back.

    Code (Text):
    1. // #pragma config statements should precede project file includes.
    2. // Use project enums instead of #define for ON and OFF.
    3.  
    4. // CONFIG1L
    5. #pragma config PLLDIV = 1         // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
    6. #pragma config CPUDIV = OSC1_PLL2 // System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
    7. #pragma config USBDIV = 1         // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
    8.  
    9. // CONFIG1H
    10. #pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
    11. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    12. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
    13.  
    14. // CONFIG2L
    15. #pragma config PWRT = ON        // Power-up Timer Enable bit (PWRT enabled)
    16. #pragma config BOR = ON         // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
    17. #pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
    18. #pragma config VREGEN = ON      // USB Voltage Regulator Enable bit (USB voltage regulator enabled)
    19.  
    20. // CONFIG2H
    21. #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
    22. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
    23.  
    24. // CONFIG3H
    25. #pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    26. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
    27. #pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
    28. #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
    29.  
    30. // CONFIG4L
    31. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    32. #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
    33. #pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
    34. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
    35.  
    36. // CONFIG5L
    37. #pragma config CP0 = ON         // Code Protection bit (Block 0 (000800-001FFFh) is code-protected)
    38. #pragma config CP1 = ON         // Code Protection bit (Block 1 (002000-003FFFh) is code-protected)
    39. #pragma config CP2 = ON         // Code Protection bit (Block 2 (004000-005FFFh) is code-protected)
    40. #pragma config CP3 = ON         // Code Protection bit (Block 3 (006000-007FFFh) is code-protected)
    41.  
    42. // CONFIG5H
    43. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
    44. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
    45.  
    46. // CONFIG6L
    47. #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
    48. #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
    49. #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
    50. #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
    51.  
    52. // CONFIG6H
    53. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
    54. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
    55. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
    56.  
    57. // CONFIG7L
    58. #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
    59. #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
    60. #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
    61. #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
    62.  
    63. // CONFIG7H
    64. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
    65.  
     
  2. Vindhyachal Takniki

    Thread Starter Member

    Nov 3, 2014
    349
    6
    Updated the settings. Since I have to port code from AT89C51, so I conected 4Mhz crystal with 33pf load caps.
    Kept settings so that system clock is 4Mhz, which make instruction cysle as 1us same as when 12Mhz crystal is connected to AT89C51.
    Also timer clocks comes out to be 1Mhz, so much easier to configure timer know.
    Also USB clock is set to 48Mhz.

    Are these settings ok?

    Code (Text):
    1. // #pragma config statements should precede project file includes.
    2. // Use project enums instead of #define for ON and OFF.
    3.  
    4. // CONFIG1L
    5. #pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
    6. #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
    7. #pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
    8.  
    9. // CONFIG1H
    10. #pragma config FOSC = XTPLL_XT  // Oscillator Selection bits (XT oscillator, PLL enabled (XTPLL))
    11. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    12. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
    13.  
    14. // CONFIG2L
    15. #pragma config PWRT = ON        // Power-up Timer Enable bit (PWRT enabled)
    16. #pragma config BOR = ON         // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
    17. #pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
    18. #pragma config VREGEN = ON      // USB Voltage Regulator Enable bit (USB voltage regulator enabled)
    19.  
    20. // CONFIG2H
    21. #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
    22. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
    23.  
    24. // CONFIG3H
    25. #pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    26. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
    27. #pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
    28. #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
    29.  
    30. // CONFIG4L
    31. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    32. #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
    33. #pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
    34. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
    35.  
    36. // CONFIG5L
    37. #pragma config CP0 = ON         // Code Protection bit (Block 0 (000800-001FFFh) is code-protected)
    38. #pragma config CP1 = ON         // Code Protection bit (Block 1 (002000-003FFFh) is code-protected)
    39. #pragma config CP2 = ON         // Code Protection bit (Block 2 (004000-005FFFh) is code-protected)
    40. #pragma config CP3 = ON         // Code Protection bit (Block 3 (006000-007FFFh) is code-protected)
    41.  
    42. // CONFIG5H
    43. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
    44. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
    45.  
    46. // CONFIG6L
    47. #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
    48. #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
    49. #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
    50. #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
    51.  
    52. // CONFIG6H
    53. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
    54. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
    55. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
    56.  
    57. // CONFIG7L
    58. #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
    59. #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
    60. #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
    61. #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
    62.  
    63. // CONFIG7H
    64. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
     
  3. dannyf

    Well-Known Member

    Sep 13, 2015
    1,811
    362
    what do they look comparing to the clock tree in the datasheet?
     
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