pic18f24k20 RA5 stuck low?

Discussion in 'Embedded Systems and Microcontrollers' started by bug13, Jun 15, 2016.

  1. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
    1,208
    38
    Hi guys

    I am working with this chip pic18F24K20, the PORTAbits.RA5 seem to stuck low?? Any secret setting that I don't know about? here is my simple test code:
    Code (Text):
    1.  
    2. while(1)
    3. {      
    4.         CLRWDT();
    5.         TRISAbits.TRISA5 = 1;
    6.         TRISBbits.TRISB5 = 0;
    7.         if (PORTAbits.RA5)
    8.             LATBbits.LATB5 = 0;
    9.         else
    10.             LATBbits.LATB5 = 1;
    11. }
    I should have disable all other function on RA5:
    Code (Text):
    1.     HLVDCONbits.HLVDEN = 0;     // disable high/low-voltage detection
    2.     SSPCON1bits.SSPEN = 0;      // disable ssp
    3.     CM2CON0bits.C2ON = 0;       // disable comparator 2
    4.     ADCON0bits.ADON = 0;        // disable ADC
    here is my config:
    Code (Text):
    1. // CONFIG1H
    2. #pragma config IESO = OFF           // Internal/External Oscillator Switchover bit->Oscillator Switchover mode disable
    3. #pragma config FOSC = INTIO67       // Oscillator Selection bits->Internal oscillator block, port function on RA6 and RA7
    4. #pragma config FCMEN = ON           // Fail-Safe Clock Monitor Enable bit->Fail-Safe Clock Monitor enabled
    5.  
    6. // CONFIG2L
    7. #pragma config PWRT = OFF           // Power-up Timer Enable bit->PWRT disabled
    8. #pragma config BOREN = SBORDIS      // Brown-out Reset Enable bits->Brown-out Reset enabled in hardware only (SBOREN is disabled)
    9. #pragma config BORV = 18            // Brown Out Reset Voltage bits->VBOR set to 1.8 V nominal
    10.  
    11. // CONFIG2H
    12. #pragma config WDTPS = 128
    13. #pragma config WDTEN = ON
    14.  
    15. // CONFIG3H
    16. #pragma config CCP2MX = PORTC       // CCP2 MUX bit->CCP2 input/output is multiplexed with RC1
    17. #pragma config HFOFST = ON          // HFINTOSC Fast Start-up->HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
    18. #pragma config PBADEN = OFF         // PORTB A/D Enable bit->PORTB<4:0> pins are configured as digital I/O on Reset
    19. #pragma config LPT1OSC = ON         // Low-Power Timer1 Oscillator Enable bit->Timer1 configured for low-power operation
    20. #pragma config MCLRE = ON           // MCLR Pin Enable bit->MCLR pin enabled; RE3 input pin disabled
    21.  
    22. // CONFIG4L
    23. #pragma config LVP = OFF        // Single-Supply ICSP Enable bit->Single-Supply ICSP disabled
    24. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit->Stack full/underflow will cause Reset
    25. #pragma config XINST = OFF      // Extended Instruction Set Enable bit->Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    26. #pragma config DEBUG = OFF      // Background Debugger Enable bit->Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
    27.  
    28. // CONFIG5L
    29. #pragma config CP1 = OFF    // Code Protection Block 1->Block 1 (002000-003FFFh) not code-protected
    30. #pragma config CP0 = OFF    // Code Protection Block 0->Block 0 (000800-001FFFh) not code-protected
    31.  
    32. // CONFIG5H
    33. #pragma config CPB = OFF    // Boot Block Code Protection bit->Boot block (000000-0007FFh) not code-protected
    34. #pragma config CPD = OFF    // Data EEPROM Code Protection bit->Data EEPROM not code-protected
    35.  
    36. // CONFIG6L
    37. #pragma config WRT0 = OFF    // Write Protection Block 0->Block 0 (000800-001FFFh) not write-protected
    38. #pragma config WRT1 = OFF    // Write Protection Block 1->Block 1 (002000-003FFFh) not write-protected
    39.  
    40. // CONFIG6H
    41. #pragma config WRTC = OFF    // Configuration Register Write Protection bit->Configuration registers (300000-3000FFh) not write-protected
    42. #pragma config WRTD = OFF    // Data EEPROM Write Protection bit->Data EEPROM not write-protected
    43. #pragma config WRTB = OFF    // Boot Block Write Protection bit->Boot Block (000000-0007FFh) not write-protected
    44.  
    45. // CONFIG7L
    46. #pragma config EBTR1 = OFF    // Table Read Protection Block 1->Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
    47. #pragma config EBTR0 = OFF    // Table Read Protection Block 0->Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
    48.  
    49. // CONFIG7H
    50. #pragma config EBTRB = OFF    // Boot Block Table Read Protection bit->Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
     
  2. JohnInTX

    Moderator

    Jun 26, 2012
    2,347
    1,029
    You have to set ANSEL.ANS4 = 0 to enable the digital function of RA5. It will always read 0 if you don't.
    You should set all other non analog pins to digital using ANSEL as well.
    See 10.7 Port Analog Control in the datasheet.
     
  3. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
    1,208
    38
    Thanks JohnlnTX, it fixed my problem.
     
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