Hi guys
I am working with this chip pic18F24K20, the PORTAbits.RA5 seem to stuck low?? Any secret setting that I don't know about? here is my simple test code:
I should have disable all other function on RA5:
here is my config:
I am working with this chip pic18F24K20, the PORTAbits.RA5 seem to stuck low?? Any secret setting that I don't know about? here is my simple test code:
Code:
while(1)
{
CLRWDT();
TRISAbits.TRISA5 = 1;
TRISBbits.TRISB5 = 0;
if (PORTAbits.RA5)
LATBbits.LATB5 = 0;
else
LATBbits.LATB5 = 1;
}
Code:
HLVDCONbits.HLVDEN = 0; // disable high/low-voltage detection
SSPCON1bits.SSPEN = 0; // disable ssp
CM2CON0bits.C2ON = 0; // disable comparator 2
ADCON0bits.ADON = 0; // disable ADC
Code:
// CONFIG1H
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit->Oscillator Switchover mode disable
#pragma config FOSC = INTIO67 // Oscillator Selection bits->Internal oscillator block, port function on RA6 and RA7
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit->Fail-Safe Clock Monitor enabled
// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit->PWRT disabled
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits->Brown-out Reset enabled in hardware only (SBOREN is disabled)
#pragma config BORV = 18 // Brown Out Reset Voltage bits->VBOR set to 1.8 V nominal
// CONFIG2H
#pragma config WDTPS = 128
#pragma config WDTEN = ON
// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit->CCP2 input/output is multiplexed with RC1
#pragma config HFOFST = ON // HFINTOSC Fast Start-up->HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
#pragma config PBADEN = OFF // PORTB A/D Enable bit->PORTB<4:0> pins are configured as digital I/O on Reset
#pragma config LPT1OSC = ON // Low-Power Timer1 Oscillator Enable bit->Timer1 configured for low-power operation
#pragma config MCLRE = ON // MCLR Pin Enable bit->MCLR pin enabled; RE3 input pin disabled
// CONFIG4L
#pragma config LVP = OFF // Single-Supply ICSP Enable bit->Single-Supply ICSP disabled
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit->Stack full/underflow will cause Reset
#pragma config XINST = OFF // Extended Instruction Set Enable bit->Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
#pragma config DEBUG = OFF // Background Debugger Enable bit->Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
// CONFIG5L
#pragma config CP1 = OFF // Code Protection Block 1->Block 1 (002000-003FFFh) not code-protected
#pragma config CP0 = OFF // Code Protection Block 0->Block 0 (000800-001FFFh) not code-protected
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit->Boot block (000000-0007FFh) not code-protected
#pragma config CPD = OFF // Data EEPROM Code Protection bit->Data EEPROM not code-protected
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0->Block 0 (000800-001FFFh) not write-protected
#pragma config WRT1 = OFF // Write Protection Block 1->Block 1 (002000-003FFFh) not write-protected
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit->Configuration registers (300000-3000FFh) not write-protected
#pragma config WRTD = OFF // Data EEPROM Write Protection bit->Data EEPROM not write-protected
#pragma config WRTB = OFF // Boot Block Write Protection bit->Boot Block (000000-0007FFh) not write-protected
// CONFIG7L
#pragma config EBTR1 = OFF // Table Read Protection Block 1->Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
#pragma config EBTR0 = OFF // Table Read Protection Block 0->Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit->Boot Block (000000-0007FFh) not protected from table reads executed in other blocks