PIC18F - Updating CCPR1 avoiding unexpected interrupt

Discussion in 'Embedded Systems and Microcontrollers' started by atferrari, Jun 23, 2007.

  1. atferrari

    Thread Starter AAC Fanatic!

    Jan 6, 2004
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    Micro family 18F

    Module CCP1 in compare mode against TMR1 in timer mode.

    Setting: "toggle output pin (RC2) on match" condition.

    My application currently loads alternatively CCPR1H:L with HALF_T1 and HALF_T2 and restarts TMR1. (It works OK like that).

    Trying to follow the frequent advice received, to leave TMR1 running alone and ADDING the next value to CCPR1H:L, here is my question:

    How to add the low and high bytes of next HALF_Tx, without risking to have an undesired match BEFORE both are added? In extreme cases this actually WOULD happen in my application. Tested.

    For other settings I know how to do it (changing CCP1M0) but no for "toggle on match". Any change of a single bit from CCP1M3:CCP1M0 would enter in an undesired condition, so I discarded that.

    I find this problem mentioned somewhere but no solution explained for this case.

    I want to retain the "toggle on match setting".

    Help appreciated.
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    The short answer is that you do the update in the interrupt routine right after a match. At least that is the way I've always done it.
     
  3. atferrari

    Thread Starter AAC Fanatic!

    Jan 6, 2004
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    As I say, I want to add high & low bytes to CCP1RH:L. There is a chance that when adding the first of them, CCP1 could find a match, triggering an interrupt (not desired) before the second one is also added.
     
  4. Papabravo

    Expert

    Feb 24, 2006
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    If you do the addition of high and low bytes right after the match interrupt, there is no chance of getting another match while you are doing the addition to update the register. Was my previous post unclear on this point?
     
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