PIC10F200/202/204/206

Discussion in 'Embedded Systems and Microcontrollers' started by RdAdr, Jul 26, 2015.

  1. RdAdr

    Thread Starter Member

    May 19, 2013
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    Question 1
    In the datasheet, at the Sleep instruction it says that:
    Status affected: RBWUF
    And then RBWUF is unaffected.

    Is this a mistake?


    Question 2
    In the datasheet, at chapter 9, at the configuration word, it says that bits 1-0 are reserved as '0'. But in the "PIC10F200/202/204/206 Memory Programming Specifications" at the config word section it says that bits 1-0 are unimplemented and reads as '1'.
    So it is '0' or '1'?

    Question 3
    At section 9.3 Reset in datasheet, table 9-1.
    It says:
    "Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory."
    So 7,6,5,4,3,2 => 6 bits. But the calibration value has 7 bits in the OSCCAL register.
    And from the table I could also see "qqqq qqqu". So 7 bits.
    So why <7:2>?


    Question 4
    In the datasheet, at the oscillator configuration section it says that:
    "This calibration value is programmed as a MOVLW xx instruction where xx is the calibration value and is placed at the Reset vector. "

    The instruction is placed at the highest location in memory. And the reset vector is at 0x000. Why does it say that it is placed there at the reset vector?

    And what is with the reset vector? I know that when the processor is started it goes to the reset vector, and this reset vector points to the first instruction to execute. But in the PIC, the PIC goes to the highest location and executes it and then wraps around to the reset vector. And then it executes this reset vector. But what does this reset vector points to?

    Question 5
    At section PowerOnReset it says:
    "To take advantage of the internal POR, program the GP3/MCLR/VPP pin as MCLR and tie through a resistor to VDD, or program the pin as GP3"

    And then at section DeviceResetTimer it says:
    "Programming GP3/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases."

    So it is required or not to program the GP3/MCLR/Vpp as MCLR?


    Thanks!
     
    Last edited: Jul 26, 2015
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    I would call it "emphasis" that RBWUF is unaffected.

    Yes. It's one or zero. And since they are unused bits it matters not which way they are unused.


    Looks like a typo to me.

    The very first instruction is at the very top of memory and is there so the OSCCAL can be loaded. The instruction counter wraps back to zero after this is loaded and it is up to the programmer to actually use that value, or not.

    Why? Maybe just for historical reasons or to have a standard place to hide away the OSCCAL value.


    It's not required to program GP3/MCLR/Vpp as MCLR, you may also program it as GP3. But you cannot program it as Vpp as that is a hardware function used only at programming time.
     
  3. JohnInTX

    Moderator

    Jun 26, 2012
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    1) Ignore references to RBWUF, its not implemented on the 10F20x. RBWUF stands for portB Wake Up Flag. This is a cut and paste error in the datasheet.
    2) I don't know. Looks like a discrepancy in the documentation. If you fully specify the chip config it will program OK however.
    3) <7,2> looks like a typo. OSCCAL is 7 SigBits with the LSbit controlling the clock output of the internal oscillator.
    4) The real reset vector is at the end of ROM as in all baseline PICs. The MOVLW xx (oscillator trim) is stored there (0FFh / 1FFh) and code execution starts there. W is loaded with xx and the PC rolls over to 000h where you can store it using MOVWF OSCCAL as the instruction at 000h. This makes the effective RESET address 000 but I agree its confusing. Keep in mind that whatever you use to program the chip must first read and save this value, erase the chip then restore the value when programming the new code. Microchip programmers do this for you. Some knock-offs may not.
    5) This refers to two different things - If you use MCLR/ as an input, you have to have a pullup. If you program it as GP3, the reset is internal. Either way, the POR still works.

    EDIT: Dang, ErnieM beat me to it.
    Great post, though! You actually read the datasheet and post questions with references???!!:) Awesome!
     
    Last edited: Jul 26, 2015
  4. RdAdr

    Thread Starter Member

    May 19, 2013
    214
    1
    Thanks for the answers. Really helping.

    The first question is a cut and paste error. Ok. I understand.

    Question 2
    I can accept the fact that this is just a discrepancy in the documentation but I cant accept "It's one or zero. And since they are unused bits it matters not which way they are unused."
    I know they are unused bits so, practically, it doesnt matter. But still. If I, out of boredom, want to read them, what will I get? A one or a zero? Anyway, I will tell my mind that is just a discrepancy and leave it like this.

    Question 3
    Ok. Its a typo. So it should be <7:1>.
    But JohnlnTX says "OSCCAL is 7 SigBits with the LSbit controlling the clock output of the internal oscillator.".
    But OSCCAL is 8 bits with the LSB (FOSC4) controlling the the clock output of the internal oscillator. THe 7 bits that you talk about is the callibration value. Right?
    Or is it something that I dont know? Maybe the LSB of the calibration value (bit 1 of OSCCAL) has some special meaning in that it controls the clock output of the internal oscillator? You lost me here.

    Question 4
    I've understood what both of you said. And I agree.
    But still, I have a problem with the datasheet because, on one hand, it says: "This calibration value is programmed as a MOVLW xx instruction where xx is the calibration value and is placed at the Reset vector. "
    And on the other hand, it says (section Program Memory) that the reset vector is placed at 0000h.
    Thus, from these two "hands" I draw the conclusion that the calibration value is placed at the 0000h location (but it is actually placed at the highest location).
    Is this a mistake from the datasheet?

    PS: in the wikipedia it says: "The reset vector is a pointer or address, where the CPU should always begin as soon as it is able to execute instructions."
    After seeing this PIC, i see that the reset vector is not necessarily a pointer to some other instruction in the memory, but it can be an instruction itself (like this MOVLW xx). Right?
     
  5. JohnInTX

    Moderator

    Jun 26, 2012
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    The documentation is contradictory so you can either read it and see, post a ticket with Microchip support and ask them or ignore it. One possible source of confusion is that Microchip started programming consistent default values for unused bits in the config word that may have been different than originally to support possible future enhancements. This would show up if you were comparing .HEX files from different versions of MPASM. If you are still curious, ask uCHIP or experiment. Its FAR more important to understand the bits that ARE implemented and specifically configure ALL of them using proper __CONFIG directives or #pragmas (not absolute values) for proper operation.

    7 SigBits as in 7 significant bits <7,1> assigned to trimming the oscillator. The remaining bit, the LSbit in OSCCAL, determines whether the PIC's clock is output on GP2 (divided by 4 which gives the basic cycle time of the PIC) or whether the pin is used for IO.

    You are splitting hairs unnecessarily. The datasheet says that 000h is the effective reset vector i.e. the first location you can use for actual code as the hardware reset vector (0ffh/1ffh) is reserved for the oscillator trim value. Start coding at 000h knowing that after reset, W contains a value that you set or clear the LSbit to control GP2 and write it to OSCCON.
     
    Last edited: Jul 27, 2015
  6. RdAdr

    Thread Starter Member

    May 19, 2013
    214
    1
    Thanks a lot. Now all is clear. :D
     
  7. RdAdr

    Thread Starter Member

    May 19, 2013
    214
    1
    I have another question with section 9.3.1. This might sound like a dumb question.
    I attached two pictures.

    The datasheet says:
    "When programmed (MCLRE = 0), the !(MCLR) function is tied to the internal VDD and the pin is assigned to be a I/O. "
    PS: By !, I mean active-low.

    And ok, If I go to config word, I see that for MCLRE = 0 => the pin functions as I/O.

    So, I drew this in the first picture. But if !(GPWU) = 1 (so that wake-up on bit change is disabled from option register), and MCLRE = 0,
    then the AND gate receives 1 and 1 (thats an inverter, not a buffer because of the little circle).

    Thus the AND gate gives 1 at the output. Thus, the pMOS is OFF. That is a pMOS because of the little circle.

    I know that if I apply a '1' on the gate of nMOS, then it is ON, and if I apply "0", then it is OFF.
    With pMOS is inverse. If I apply "0" it conducts and if I apply "1" then is OFF.

    So, what is happening here?
     
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  8. JohnInTX

    Moderator

    Jun 26, 2012
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    The figure is not intended to be a complete schematic - rather, its a functional diagram, and not a complete one, just enough to illustrate this particular function. For example, Fig 9.2 shows GP3/MCLR- in a different way. The point there is to illustrate the on chip reset.

    The MOS device shown is not a necessarily a discrete FET so PMOS/NMOS analogies don't work. Consider it an analog switch. Its function is to apply an internal pullup to MCLR/ when MCLRE=0 (disables pin or MCLR) OR GPWU/ is 1 (disables wake up on pin change). When none of these options is selected, the pin is a general purpose input controlled by GP3.
     
  9. RdAdr

    Thread Starter Member

    May 19, 2013
    214
    1
    Thanks for the answer.

    It is an AND there. So:
    "Its function is to apply an internal pullup to MCLR/ when MCLRE=0 (disables pin or MCLR) AND GPWU/ is 1 (disables wake up on pin change)."

    Right? MCLR/ gets pulled up (internally tied to Vdd) if MCLRE = 0 AND GPWU/ = 1. So I should see that MOS device as an nMOS, even though the analogy doesnt work?
    I understand it is just a functional diagram. But still, it should behave correctly.
    If is an OR there, they should have put an OR gate. Or if they decided to put MOSes there, they should have put an nMOS.

    And I dont see that figure 9.2 shows GP3/MCLR in a different way. I still see this pin connected to the OR gate. And I still see the MCLRE connected to the OR gate through the NOT gate.
     
    Last edited: Jul 28, 2015
  10. JohnInTX

    Moderator

    Jun 26, 2012
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    Its a NAND function where any 0 on the input (GPWU = 0 OR MCLRE=1->0) puts a 1 on the analog switch, turning on the internal pullup.

    But you don't see GPWU/, the pullup or its control... Different.

    Look, its pointless to try to derive gate-level detail from these figures and totally unnecessary. Read the description of the various chip features, flip bits in the chip's CONFIG or SFR registers to control them and get on with it.
     
    ErnieM likes this.
  11. RdAdr

    Thread Starter Member

    May 19, 2013
    214
    1
    I really appreciate the help but.
    In the first post you say that internal pullup is applied if MCLRE = 0 or GPWU/ = 1.
    In the second post you say the internal pullup is applied if MCLRE = 1 or GPWU = 0. (and at GPWU i dont know if you forgot the slash / or not)

    It doesn't make sense.

    And, yes, I dont see GPWU/, the pullup or its control because maybe is not relevant for the on-chip reset. But this doesnt mean that they are not there. Only that they are out of the picture. If all was put in the picture then it would have taken too much space. I also dont see the flash memory but this doesnt mean that the flash is not there somewhere.
     
  12. JohnInTX

    Moderator

    Jun 26, 2012
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    They're typos. I guess I get sloppy in pedantic discussions.
    Carry on.
     
    ErnieM likes this.
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