PIC MCU instruction cycle Q1, Q2, Q3, Q4. What's happening?

Discussion in 'Embedded Systems and Microcontrollers' started by ke5nnt, Mar 28, 2013.

  1. ke5nnt

    Thread Starter Active Member

    Mar 1, 2009
    384
    15
    Broadly speaking, I'd like to know what's happening on each Q of a microcontroller's clock cycle.
    What I do know is that the oscillator frequency used is divided by the MCU circuitry to make 4 oscillator pulses equal 1 instruction cycle. I know that each instruction is fetched, decoded, and executed, and that one instruction cycle is used to fetch, and a second to execute. What I don't know is, are separate things happening in each Q that make it so this setup is required?

    I'm probably phrasing my question horribly. Is Q1 used to fetch the instruction's program memory address and load it into the program counter, then Q2 does what? Q3 and Q4?
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    It depends on the instruction. Some instructions take an extra clock to finish, others only one. Being a RISC processor, the instruction is guaranteed* to finish within this one instruction cycle, regardless of the instruction executed. This way, the timing of the program is able to be relatively closely predicted.

    *This is not always true, there are exceptions like in a branch statement.
     
  3. Markd77

    Senior Member

    Sep 7, 2009
    2,803
    594
    Have a look at the instructions section in PICmicroTM Mid-Range MCU Family Reference Manual


    ww1.microchip.com/downloads/en/devicedoc/33023a.pdf
     
  4. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,395
    1,607
    Look at your data sheet for "CLKOUT AND I/O TIMING"

    Generally they do something like so:

    Q1: Fetch the current instruction
    Q2: Read the data for current instruction
    Q3: Execute the current instruction (ie, add/shift/subtract/test data)
    Q4: Write any data for the current instruction

    Note if a jump is required two Q1-Q4 cycles are required when the "jump to" address instruction is loaded at the next Q1 cycle.
     
  5. ke5nnt

    Thread Starter Active Member

    Mar 1, 2009
    384
    15
    Thank you all. Appreciate the responses as always.
     
Loading...