Phase locked loops

Discussion in 'Homework Help' started by samski, Nov 23, 2011.

  1. samski

    Thread Starter New Member

    Nov 23, 2011
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    Hi. So I thought I understood PLLs pretty well after I designed a couple over summer, but I've just been taught them at university and I'm now pretty stumped! The lecture notes use Phasors which just make things confusing. I wonder if anyone could explain the 2 initial setup equations used in my notes?

    Here are the notes:
    [​IMG]

    please note that my big confusion is because of the possible mixing of phasors and phases, so it would be awesome if you could try and be clear between the two.

    Any help would be really appreciated,

    Cheers,

    Sam
     
  2. steveb

    Senior Member

    Jul 3, 2008
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    I think there are two things contributing to your confusion.

    First, they chose to use the variable theta (or maybe it's a phi) for the phasors, and then they use the same symbol for the phase angle itself. That's a bad practice.

    Second, they decided to normalize the magnitude of the phasors to a value of one, which further disguises the fact that phasors are not phase angles.

    Think of the phasors as high frequency voltages that just happen to have a magnitude of one. The units would typically be Volts, but there is no law that a PLL can't be made using another variable like current or a mechanical variable, like position. But, most PLLs we see in practice are voltage based signals, or they are mathematical entities with arbitrary units in a digital PLL. Phase angles have units of radians (or degrees if you prefer), and they are completely different animals in this context.
     
  3. samski

    Thread Starter New Member

    Nov 23, 2011
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    Agreed on both counts haha, I shan't mention which fairly well known uni this is from ;)
    So in equation (1) it would make sense to me if he were using phasES, but later in the maths they are factorised in with other thetas that are eventually converted back to exponential (a.k.a. the theta's in equation 1 are phasORS). Any ideas how this one works? Why does subtracting 2 sinusoids find their difference in phase? I thought a phase detector normally worked by mixing signals.
    EDIT: actually I think I'm fine with this, I can't quite remember how to make the phasor maths work for subtraction, but the concept of removing one phasor from the other is cool.

    OK, so equation (2). Frequency is rate of change of phase, but then why does he seem to differentiate the phasOR? Thats differentiating e^j(wt+theta). Which I can't see how it achieves a frequency...

    Annoying, I could explain how a PLL works using sum and differences in sines, but I couldn't use that to get the big differential equation that were supposed to get to by the end, so we can draw impulse responses etc.
     
    Last edited: Nov 24, 2011
  4. steveb

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    Jul 3, 2008
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    I have to say that I agree with your confusion on eq 1 for the phase error. I would not have expected a simple subtraction on the phasors to generate a phase detection.

    I'm just waking up and I have to help my wife get a turkey in the oven, but a little later i'll have a few minutes to write up some equations and scan through a book I have on pll design.
     
  5. steveb

    Senior Member

    Jul 3, 2008
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    So far, I can't resolve this issue. This leads me to believe that the block diagram model you showed might be a converted or transformed model, and perhaps those phasors really are "phase" signals themselves. I need to think about this more (hopefully someone else will join in), but I just wanted to warn you that my first response might end up being off base. If the block diagram is a transformed version of the system, then one needs to figure out the methodology in making the transformation.
     
  6. steveb

    Senior Member

    Jul 3, 2008
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    Ah, ok, it just hit me. I should have realized that the use of the frequency domain might imply that a linearized model has been used here. Normally, the PLL is a nonlinear system, but for small deviations in phase, one can make a linearized model using the phase as the signal of interest. That should be the key to understanding your block diagram.

    Here is a reference that mentions frequency domain linearized models.

    http://www.ti.com/lit/an/slyt169/slyt169.pdf

    EDIT: By the way, my gut feeling is that the phase signals themselves should have an amplitude associated with them. The units of amplitude are radians (or degrees), but the whole idea of the frequency domain analysis is to look at the magnitude and phase response of the system. The fact that the system happens to have angles as inputs and outputs shouldn't change this. I could be wrong because we are not looking at the full development of the full model and the transformation to the phase signals, but that's my best guess.
     
    Last edited: Nov 24, 2011
  7. samski

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    Nov 23, 2011
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    hang on, so are we saying that omega is the difference/beat frequency?
     
  8. steveb

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    If what I'm saying is correct (which still needs to be verified) then omega is a hypothetical small signal variation in the phase signal itself. We can imagine deliberately putting a small ac signal on the phase angle and determining the magnitude and phase response, derived from an H(s) for the system.
     
  9. samski

    Thread Starter New Member

    Nov 23, 2011
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    staring at it more in this way is making more sense (esp the phase detector). The VCO equation sort of makes sense, but differentiating phase for frequency generally requires the phase to be an increasing function, e.g. phase=10t, frequency=d(10t)/dt=10. So you are probably also right about missing terms of amplitude in the phasors.

    You are further justified, as the equations that follow for the filter use omega for the impedance of the capacitor, 1/(jwc) (something that previously made things more confusing).

    I can't believe the lecturer left this so ambiguous even after I e-mailed him and specifically said "So I think my confusion was more with what omega represents. Is it the input frequency to the PLL?", bah humbug.
     
    Last edited: Nov 24, 2011
  10. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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    The attached simulation schematic is meant to show the concept of an analog phase detector using a simple multiplier and LPF combination.

    I thought it might be informative to see how the phase difference value might be detected in a simple analog situation.

    The two inputs V1 and V2 are two 1000Hz sine-wave signals whose phases are to be compared. V1 & V2 are identical except for their phase difference of 45°.

    The measured output phase is 'interpreted' in relation to the mean value of the multiplied signal. In this situation the measured phase signal turns out to be related to the cosine of the phase difference value. So it's a non-linear phase detector but that's not particularly important here.

    What one sees that is probably worth noting, is that the phase difference signal is a DC offset sinusoid at twice the input frequency. One therefore has a DC value corresponding to the phase error with some superimposed AC signal - which one would notionally want to reduce to as small a value as possible whilst preserving the PLL response & stability. Also the superimposed AC on the phase detection signal ultimately finds its way back to the VCO input and introduces phase jitter.

    The amplitude of the superimposed sinusoid is in turn related to both the LPF cut-off frequency and the actual phase error. The mean value is always related only to the actual phase difference.
     
    Last edited: Nov 24, 2011
  11. steveb

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    Jul 3, 2008
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    Yes, this is informative and brings back the memories of studying this years ago. The remaining nonlinear system is the VCO itself and this can be modeled in a simple way as follows, where wo is a nominal frequency output, K is a constant that defines the frequency control sensitivity, and phi is some arbitrary initial phase condition.

    V_o=\sqrt{2} \cos ((\omega_o+K\;V_2)t+\phi)

    With all nonlinear systems defined, one can linearize in terms of phase and then develop a frequency domain model along the lines given above. It would then be clear if the given model is suitable, or if there is a mistake in the presentation. My gut feeling is that what is given is essentially correct, but that there might be a mistake or two that is causing confusion. But, the only way to tell for sure is to look it up, or to work it out.

    I'm tempted to work this out tonight, but I'm pretty sure my PLL book is at work and I'll be there tomorrow. I'll look there and post a few pages if I think they are helpful in clearing up any confusion that the OP has due to being given an inadequate foundation on the subject.
     
  12. samski

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    Nov 23, 2011
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  13. samski

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    Nov 23, 2011
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    Yes, this is helpful for understanding. I'm aware of the DC offset which is proportional to the input frequency. This does not appear in the notes, (essentially if there is no 'wobble' in the input phase then the output frequency is 0, according to equation 2) so is the neglection of it acceptable? I feel the input phase should be of the form: 2*pi*ft+e^(jwt), differentiating (differentiation of phase should be frequency), and assuming no wobble (w=0) gives: 2*pi*f which IS the frequency. So V2 would be = 2*pi*f/K
     
  14. steveb

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    Jul 3, 2008
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    This morning I got into work and found my old PLL book. This book is "Phase-Locked Loops, Design, Simulation and Applications", 3rd edition, by Roland E. Best. I think it is a very good book by the way. The second chapter effectively lays out exactly what you are trying to do.

    What I see here is that the block diagram from your class pretty much matches up with the linearized phase domain model from the book. However, phasors are not mentioned at all, and this seems to be the thing that is confusing to both you and me. So, I recommend just ignoring the phasor formulas that you have. They don't seem to do anything useful. We can certainly think in terms of the frequency s-domain because the model is a linearized model, and the s-domain implies a phasor like description of the inputs and outputs, but the way your Prof. writes it out seems confusing. There is room to get confused with the frequency from the Laplace s-variable, as compared to the VCO output frequency, and it's not clear to me why the phasor should not have an amplitude to capture the magnitude response. The real reference signal and output signal (represented as voltage sine waves) might have a fixed amplitude, but it's not clear why the the phasor should have a fixed amplitude if it is representing the linear domain signal, and not the full nonlinear signal. If those phasors are supposed to represent the real voltage signals, then the amplitude of one would be acceptable, but then he should not say that the output of the phase detector is simply the subtraction of the two phasors.

    If you want me to scan and post some pages from the book, I'm willing to do that.
     
  15. t_n_k

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    The attached application note has quite a good treatment of the PLL and the formulation of the linearized transfer function.
     
  16. samski

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    Nov 23, 2011
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    thanks for that both.busy weekend and 10 page report in on thursday is keeping me away from this. hope you had a good thanksgiving.

    so equations 4 and 5 are really puzzling to me in the attachment t_n_k gave. how can you say "for e_f = 0, Let differential of theta_2 = omega*theta". when equation 4 directly links the two.

    i see this as like saying x=y. for x=0, let y=5.
     
  17. t_n_k

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    Yes you are correct - there is a typo in the AN46 text at equation [4]
    The text should read.

    for \ e_f=0, \  let \ \dot{ \theta_2}=\omega_0 \ then
     
  18. samski

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    Nov 23, 2011
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     \ \dot{ \theta_2} (t) = \ K_0 \ e_f
     \ e_f = 0
     \ \dot{ \theta_2} = \omega_0

    so  \omega_0 = 0 ?
     
  19. t_n_k

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    I guess the implication is that the VCO output time varying phase is given by

    \theta_2=(\omega_0+K_0e_f)t

    which leads to

    \dot{\theta_2}=(\omega_0+K_0e_f)

    So the writer has perhaps been somewhat inconsistent ('sloppy'?) with his notations. Perhaps he thought this was so obvious it didn't require any elaboration.

    What the last relationship itself implies is that with the loop in lock and with the assumed condition

    \theta_1(t)-\theta_2(t)=0

    then the consequent result ef=0, leads one to the reasonable / necessary conclusion that θ2 is advancing at the same rate as θ1 at ω0 radians per second - otherwise the loop can't be in lock.

    To some extent this must all be interpreted in the light of the entire closed loop structure. For instance, the properties of the filter will have a significant impact on the reality or otherwise of whether the condition

    \theta_1(t)-\theta_2(t)=0

    is met under steady-state locked conditions. In practice, unless the filter (or other undisclosed additional loop compensation) includes a 'DC' integrating 'term' then one cannot achieve zero steady-state phase error with the loop structure. Notwithstanding this, one can still envisage the loop in locked condition with the proviso that the steady state phase error is non-zero but constant - thereby implying the lock condition is still true. In phasor 'jargon' we may think of the signal phasors [for ei and eo] as being displaced in angular position but locked in their angular rotational frequency.

    In principle I think this means that one must therefore meet a minimum 'steady-state' requirement that

    \dot{\theta_1}(t)-\dot{\theta_2}(t)=0

    to achieve a locked condition.
     
    Last edited: Nov 29, 2011
  20. samski

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    Nov 23, 2011
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    boom! think I've sussed it. I'll scan stuff in later today

    here it is: http://dl.dropbox.com/u/38907387/PLLmaths.pdf If you can spot any errors in it before I sent it to my lecturer & make an arse of myself, that would be super.

    Cheers

    Sam
     
    Last edited: Dec 1, 2011
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