What is this circuit supposed to do?

My thoughts exactly. It's unusual to vary a current source using sine and square waves. I also wonder about the purpose of the capacitor and the 10 and 1K resistors.

 

I also wonder about the purpose of the capacitor and the 10 and 1K resistors.

They are needed to prevent circuit from oscillations. Do not forget that the MOS gate is just a "big" capacitor and op-amps do not like a capacitors load.
And this circuit is a standard solution for the capacitor load problem.

 

They are needed to prevent circuit from oscillations. Do not forget that the MOS gate is just a "big" capacitor and op-amps do not like a capacitors load.
And this circuit is a standard solution for the capacitor load problem.

Thanks for the info. What happens if you short R2 and R4?

 

Thanks. I wasn't thinking about what the current source was doing...

A diode connected as you mentioned will help with the saturation, but it won't eliminate it. The OP needs to prevent the input from going negative.

It will eliminate saturation as long as the input stays within the common-mode range of the op amp.
The diode maintains negative feedback and keeps the op amp in its active region so it doesn't saturate.

 

Ok here are new tests summarized in the attached PDF with some extra stuff showing power supply connection if anybody objects that.
All compensatory elements are removed so that nobody can object that as a source of a problem The circuit worked fine for the test, but not in all setups
Input is sine 10kHz Vp=25mA amplitude
Placing diode as suggested makes definitely a difference, the step is smaller !
Also, I replaced MOSFET with NPN, and that also makes the smaller step. Setup with NPN and diode works the best.

So what would be now explanation of the visible step when the op-amp is prevented from going into saturation?
What about P-N or Gate-Source capacitance?
For example, as the op-amp output voltage rises from -0.7V, the charging current for gate-source capacitance flows from the op-amp through the sense resistor (1 ohm), but not through the load. Then op-amp detects voltage across sense resistor and work fine ("thinking that proper current is set"), but that doesn't create any current through the load until gate-source capacitance is charged to 5-6V and that is why there is a step across the load. Does this sound reasonable?

Also, I disconnected power supply/regulator and left connected only 3x200uF letting them fully discharge while keeping -+12V power and also signal generator connected. To my surprise I was able to measure non-zero voltage peaks across the load as somehow capacitors are being charged in sync with the 10khz input signal (see figure)
This also can be seen across the sense resistor, no surprise (see figure).
How to explain the voltage changes across the 3x200uF caps and can this be an issue contributing to the "step"?

 

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So what would be now explanation of the visible step when the op-amp is prevented from going into saturation?

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From my simulations it would appear that the op amp response time is the problem. The output is slewing much slower than the slew rate would indicate (≈1-2V/μs).
That may be because the op amp GBW also is affecting the response time.

I think the only way to totally eliminate the problem is to bias the circuit with a few mA minimum current through the load.
You could sum a small voltage into the op amp using a pot to adjust the quiescent current value.

 

Ok here are new tests summarized in the attached PDF with some extra stuff showing power supply connection if anybody objects that.
All compensatory elements are removed so that nobody can object that as a source of a problem The circuit worked fine for the test, but not in all setups
Input is sine 10kHz Vp=25mA amplitude
Placing diode as suggested makes definitely a difference, the step is smaller !
Also, I replaced MOSFET with NPN, and that also makes the smaller step. Setup with NPN and diode works the best.

So what would be now explanation of the visible step when the op-amp is prevented from going into saturation?
What about P-N or Gate-Source capacitance?
For example, as the op-amp output voltage rises from -0.7V, the charging current for gate-source capacitance flows from the op-amp through the sense resistor (1 ohm), but not through the load. Then op-amp detects voltage across sense resistor and work fine ("thinking that proper current is set"), but that doesn't create any current through the load until gate-source capacitance is charged to 5-6V and that is why there is a step across the load. Does this sound reasonable?

Also, I disconnected power supply/regulator and left connected only 3x200uF letting them fully discharge while keeping -+12V power and also signal generator connected. To my surprise I was able to measure non-zero voltage peaks across the load as somehow capacitors are being charged in sync with the 10khz input signal (see figure)
This also can be seen across the sense resistor, no surprise (see figure).
How to explain the voltage changes across the 3x200uF caps and can this be an issue contributing to the "step"?

It may be a combination of things, but one to look at is the gate charge of the FET. Since the op amp is in the wrong state and the FET turned completely off the op amp has to drive the gate to the threshold. Let's say the FET has a gate charge of 50 Nc and the max current for the op amp is 50 ma. it could take quite a while to turn it on again. A logic level FET might speed things up a little bit since the voltage wouldn't have to rise quite so high.

 

It may be a combination of things, but one to look at is the gate charge of the FET. Since the op amp is in the wrong state and the FET turned completely off the op amp has to drive the gate to the threshold. Let's say the FET has a gate charge of 50 Nc and the max current for the op amp is 50 ma. it could take quite a while to turn it on again. A logic level FET might speed things up a little bit since the voltage wouldn't have to rise quite so high.

So do what Zapper suggested; never turn the FET off... always keep the FET conducting...

 

Or, do it the old fashion way and use a Bipolar junction transistor instead of a FET.

 

Or, do it the old fashion way and use a Bipolar junction transistor instead of a FET.

The OP posted the results of that in Post #25.
It helped the problem but didn't eliminate it (since the op amp still has to slew a minimum of about 1.4V between the negative clamp and the positive turn-on of the transistor.

 

The OP posted the results of that in Post #25.
It helped the problem but didn't eliminate it (since the op amp still has to slew a minimum of about 1.4V between the negative clamp and the positive turn-on of the transistor.

Yes, that & the gate capacitance.

 

Thanks for all your replies. AD848 is pretty fast 300V/us and GBW 175Mhz so I would say its current capacity to drive capacitive load limits the output rise time.

@ronv Yes thinking as that it all makes sense! The MOSFET that I'm using has actually ~70nC gate charge for threshold voltage
Current = Charge/time -> time = 70e-9/50e-3 > 1us !!

I will test couple of different scenarios. NPN will be straightforward, but I do not prefer them . Other possible solutions could be a current buffer on the op-amp output or to keep the output near the MOSFET threshold

 

Why don´t you first use a precision half wave rectifier to get rid of the negative part of the signal, then bias the output such that the opamp doesn´t go into saturation with zero input voltage?

 

Why don´t you first use a precision half wave rectifier to get rid of the negative part of the signal, then bias the output such that the opamp doesn´t go into saturation with zero input voltage?

I cannot bias the op-amp. The current has to be 0 and only non-zero through the load when there is a signal

 

I cannot bias the op-amp. The current has to be 0 and only non-zero through the load when there is a signal

Without a small bias current I don't think you can readily get there from here.
Are you sure you can't tolerate a small bias such as 10μA?