PCB Layout Review

Discussion in 'The Projects Forum' started by jwilk13, Nov 14, 2011.

  1. jwilk13

    Thread Starter Member

    Jun 15, 2011
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    Hello,

    I recently did a design project, and I did a rough mock-up of the design with perf-board, but I would like to turn that mock-up into a nice PCB. I don't have much experience in this area, so I was hoping I could get some feedback on the layout I put together. I have attached images of the layout I made (all done in Eagle).

    I guess my main concerns are with EMI/EMC and with U5 (shown in layout). U5 is a current monitor, so it senses small voltages across R1 and amplifies it according to the values of R12, R13 and R14. I'm sure this highly sensitive device can be susceptible to noise, and I don't know if my layout would cause any problems with that.

    There are some things that may be of importance as well. First, the signal at H3 is a PWM output signal switching an inductive load with a frequency of 250 Hz. H1 is an unregulated DC voltage ranging from 12-24 V. H2 is system ground. U4 is the switching device; I tried to keep this as far away from my uC as I could.

    I would greatly appreciate any feedback that anyone has to offer. This is my first attempt at a board design this complex, so thanks in advance :). Also, when you click on the thumbnails, click on the image again for a full-size version (otherwise it's a bit blurry).

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  2. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    There is no U5 shown; just U1 thru U4.
    There are a couple of traces that wander off the upper edge of the board; one on the top layer, one on the bottom layer. Perhaps your U5 is up above that edge somewhere?

    You have Vss on the uC, along with the low sides of C2 and C3, connected by a thin trace to a via dead center under the uC. You would be better off to drop vias right next to the uC's two Vss pins, and route very short traces to them.

    Place C2 on one side of the uC, and C3 on the other. Make the traces from the uC to the caps very short. Use the same via as the Vdd pins for your ground side.

    It seems to me that your traces are unnecessarily long, and unnecessarily thin. The shorter and wider your traces are, the less inductance they will have, and the more compact your board will be.

    Consider moving some of the components to the other side of the board; that should help you to make the board much more compact if you can avoid routing issues.

    I am not sure why you placed D2 in the lower right corner; then ran the trace for it from the upper center of the board from R16, and R16 gets current from SOMEWHERE in the vicinity of what is labeled U4 - probably via R11 from H3, whatever H3 means. So, now it appears that D2, an LED, is being powered from a source that is in the opposite corner of the board. Does it really have to be so far away?

    You have R4 thru R9 very neatly clustered around C7. However, the centers of the dividers have a long, long way to go before they get to the uC; and those are high-impedance signals at that point. Unless you at least put some caps on those dividers, you will have a lot of noise on them. If they are ADC inputs, 10nF from the uC input pin to ground should work OK. However, consider scooting those pots/resistors a lot closer to the uC (or the other way around), and using one more cap on the +5v side along with the 10nF on the uC side to keep things quiet.

    I'm not sure why you used 10k pots and fixed 4.7k resistors for the dividers; I guess you wanted the signals to be adjustable from 0v to ~3.33v?

    You've removed the reference designators from the schematic (U1, R3, etc) so it makes it more difficult to relate the schematic to the board. At a minimum, show the reference designators (NAME field) on the board.

    You have also used some labels for wire pads that are not terribly helpful. "H3" does not have any meaning to me. +24V IS meaningful. Unfortunately, "H1" shows on the board instead of +24V.

    It will help you to help yourself if you try to make the board and schematic more self-explanatory. Just think, maybe 5 years down the road, you'll need to fix or use this project - and if you've lost the source documentation (happens every day) it'll be a lot easier if you have meaningful reference designators and notes on the board itself.

    It will also be helpful if you upload your .sch and .brd files; that way those who have Eagle installed can run additional checks for you.
     
  3. jwilk13

    Thread Starter Member

    Jun 15, 2011
    228
    12
    Thanks for the pointers :)

    U5 is actually a tiny SOT-25 package just below H3 (I used H to represent "hole", but you are right, designators would be better). D2 is simply used to show that there is PWM output, but I probably should move it up closer to the source. I am definitely going to try to move the resistive dividers closer to the uC, and I will add 10 nF capacitors near each ADC pin (you were correct in assuming they are ADC inputs, ranging from 0v to ~3.33v). I'm going to clean the schematic up as you suggested as well...I'm not sure why I didn't have the NAME fields shown on some of them.

    As always, thanks for the input.
     
  4. SgtWookie

    Expert

    Jul 17, 2007
    22,182
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    Some other things;

    Vias are very handy for not only routing signals across board layers, they are also good for moving heat between layers. I see that you have several vias under U2. I would put vias everywhere under U2, AND U3. Why throw away a perfect opportunity to more than double your cooling area?

    Keep an eye on the hole sizes. Eagle is going to complain during DRC if you have holes smaller than ~30 mils, or whatever you have set up in your rules. Check with whomever you are going to use to make your boards what the smallest hole size is.
    '
    The smaller you make the holes, the less plating material in the hole you'll have to conduct current and heat from one side to the other; so making the holes in the vias really small is self-defeating.

    Have you used ERC in the schematic editor?
    Have you run DRC in the board editor?
     
  5. jwilk13

    Thread Starter Member

    Jun 15, 2011
    228
    12
    Thanks for pointing out the via size issue. The vias under U2 were meant to transfer the heat to the bottom layer, and the much larger ground plane, but they are quite small. The board manufacturer I'm thinking about going with has a minimum drill size of 8 mils and all of mine are >12 mils. I'll definitely make the vias meant to conduct heat much larger.

    I have done both ERC and DRC, and everything checks out (after putting in the manufacturer's design limits to the DRC).
     
  6. jwilk13

    Thread Starter Member

    Jun 15, 2011
    228
    12
    Another thing, how close should the 10 nF caps be to the ADC inputs of the uC? I'm placing them right now, but I don't have a huge amount of space up close to the uC to put them. Would <0.5" work OK?
     
  7. SgtWookie

    Expert

    Jul 17, 2007
    22,182
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    The closer you put them, the better.

    Keep in mind that traces have inductance. The shorter and wider the traces are, the less inductance they will have. A 10mm long piece of paper clip wire had an inductance of about 8nH @ 15MHz when I measured it a number of years back. 8nH doesn't sound like much, but you would be surprised how quickly board parasitics like that add up.
     
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