Hi,
I am currently working on a few projects with PCB boards and I had a few questions about them. One system contains a 24 bit ADC so Im trying to think of everything to reduce noise and other problems. Right now my questions are just about ground return currents and transmission line models. So here are the questions.
Im trying to figure out if I understand ground current return loops so here are some examples and please tell me if or how I got any loops wrong.
From figure 1 when the signals are high (there are two separate PCBs, internally all the gnds are connected as well as all the Vccs through solid planes on both boards. All the signals are digital at about 1MHz, 1-6ns rise time):
Sig1: Vcc2;sig1;gnd1;gnd;Vcc;Vcc2.
Sig2: Vcc1;sig2;gnd2;gnd;Vcc;Vcc1.
IC1 Internal current use: Vcc1;IC1;gnd1;gnd;Vcc;Vcc1.
Sig3: Vcc2;sig3;gnd3;gnd;gnd;Vcc;Vcc2
For signal 3, would the proper technique be to send a gnd cable along with the signal and would this gnd cable be connected at gnd2 or gnd, does it make a difference? Where would I connect it on PCB 2, at gnd3? Would the gnd cable not introduce noise back to the ADC board, or because of the solid ground on PCB2 only ground return for signal 3 would flow in that cable and everything else would flow through its own gnd?
Im planning on routing (output) signals going to other boards such as sig3 through a logic buffer that will sit right at the boards edge. Would this help reduce noise from other boards or is there some other recommended method? Am I missing some other consideration?
To model as a transmission line; knowing that the rise time of the buffer in a 74HC package is 6ns, and using this calculator http://www.pcb123.com/help/calculators/microstrip.html to find the propagation speed in my PCB track as 0.1431 ns/in à 6.99in/ns*6ns = 41.93in/2 (div by 2 b/c of return track)= 20.96in. Alternatively, the maximum clock speed of components on PCB1 is 20MHz, then wavelength/10 = c/(f*sqrt(er)) = (299792458/(sqrt(4.5)*20000000))/10 meters = 27.81 in.
Then if the total wire and PCB track carrying sig3 is less than 20 I dont have to worry about the tracks/wire/connection not matching impedance to each other, right?
Also, for on board traces, assuming a min rise time of 1 ns (its not given from some ICs) then if the length of the trace is less than 6.99/2=3.5 then I also dont have to worry about impedance and such, right?
Another question; say I have a three layer board with 2 solid ground planes below a signal plane. Say a signal originating from Ica and going to ICb is routed on the top signal layer. Now the question is if the ground return current flowing below the signal flows on the top or bottom ground plane. I think the answer is; it depends to which plane the ground of ICb is connected to, if that ground is connected to the top layer it will flow in the top otherwise it will flow in the bottom. Is that correct?
Finally, would it be okay if I post my ADC system PCB footprints to see if anyone has comments, in a new thread?
Thanks in advance,
Matt
I am currently working on a few projects with PCB boards and I had a few questions about them. One system contains a 24 bit ADC so Im trying to think of everything to reduce noise and other problems. Right now my questions are just about ground return currents and transmission line models. So here are the questions.
Im trying to figure out if I understand ground current return loops so here are some examples and please tell me if or how I got any loops wrong.
From figure 1 when the signals are high (there are two separate PCBs, internally all the gnds are connected as well as all the Vccs through solid planes on both boards. All the signals are digital at about 1MHz, 1-6ns rise time):
Sig1: Vcc2;sig1;gnd1;gnd;Vcc;Vcc2.
Sig2: Vcc1;sig2;gnd2;gnd;Vcc;Vcc1.
IC1 Internal current use: Vcc1;IC1;gnd1;gnd;Vcc;Vcc1.
Sig3: Vcc2;sig3;gnd3;gnd;gnd;Vcc;Vcc2
For signal 3, would the proper technique be to send a gnd cable along with the signal and would this gnd cable be connected at gnd2 or gnd, does it make a difference? Where would I connect it on PCB 2, at gnd3? Would the gnd cable not introduce noise back to the ADC board, or because of the solid ground on PCB2 only ground return for signal 3 would flow in that cable and everything else would flow through its own gnd?
Im planning on routing (output) signals going to other boards such as sig3 through a logic buffer that will sit right at the boards edge. Would this help reduce noise from other boards or is there some other recommended method? Am I missing some other consideration?
To model as a transmission line; knowing that the rise time of the buffer in a 74HC package is 6ns, and using this calculator http://www.pcb123.com/help/calculators/microstrip.html to find the propagation speed in my PCB track as 0.1431 ns/in à 6.99in/ns*6ns = 41.93in/2 (div by 2 b/c of return track)= 20.96in. Alternatively, the maximum clock speed of components on PCB1 is 20MHz, then wavelength/10 = c/(f*sqrt(er)) = (299792458/(sqrt(4.5)*20000000))/10 meters = 27.81 in.
Then if the total wire and PCB track carrying sig3 is less than 20 I dont have to worry about the tracks/wire/connection not matching impedance to each other, right?
Also, for on board traces, assuming a min rise time of 1 ns (its not given from some ICs) then if the length of the trace is less than 6.99/2=3.5 then I also dont have to worry about impedance and such, right?
Another question; say I have a three layer board with 2 solid ground planes below a signal plane. Say a signal originating from Ica and going to ICb is routed on the top signal layer. Now the question is if the ground return current flowing below the signal flows on the top or bottom ground plane. I think the answer is; it depends to which plane the ground of ICb is connected to, if that ground is connected to the top layer it will flow in the top otherwise it will flow in the bottom. Is that correct?
Finally, would it be okay if I post my ADC system PCB footprints to see if anyone has comments, in a new thread?
Thanks in advance,
Matt
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