I was wondering which of the following layouts for adding a decoupling capacitor to each IC is preferred, or at least compare the options critically.

Figure 1 represent connecting the capacitor, IC pin and trace with a triangular area of copper.

Firgure 2 represents connnecting with the capacitor to the power trace with a similar wide trace.

Figure C is similar to the previous example, but a narrow trace is used.

Figure 4 puts the capacitor lead right on the power trace.

Comments?

 

I don't think it matters much, except I would avoid the one with the small trace. However, here's the way I do it.

 

I think the #4 is the correct way to connect decoupling caps. Because the trace has some resistance and inductance, the best decoupling is achieved when the power track goes first into the cap and from there to the IC pin. It forms a kind of T filter arrangement. #1 could be acceptable, #2 is wrong because this way the cap is more loosely coupled to the power pin than necessary.

Anyway, for typical logic DIP packages this almost doesn't matter, because the other leg of the cap needs to go to the lower left pin and this distance screws things up anyway.

 

There is not much difference between 1, 2 and 4.
Definitely C is not the preferred choice.
Fig 4 is preferred.
You did not show the GND connection from the IC.

 

MrChips: All IC's GND connection connects to a ground plane on the bottom layer of a double-sided PCB.

 

I say none, because you are not connecting the other supply pin to the capacitor, so it isn't doing anything at the moment

Oops I feel stupid... I have just read the post above about there being a ground on the other side of the circuit :$

 

Ok, so everyone seems to agree that Figure 4 is the way to go. Thanks to all for chiming in. I've attached an updated figure, also showing the IC's connection to the ground plane (green layer).

And I am surprised that no one commented on my warped sense of humor.

 

I generally do it similar to tracecom's example or your last one.

If I'm really fighting noise, a couple of other alternatives are to put the cap as a SMD part on the underside of the board midway between the power pins. Another tactic, which is a compromise, is to run a trace from the negative side of the cap to the ground of the part and not ground it directly to the plane. This forces the supply current to go past the bypass cap. You can get crazy (and go crazy) with this stuff. Putting decade tiered caps with the smallest two (or three) tiers at each component, the next one up in small groups of components and on up until you get to your large electrolytic bulk-storage caps that cover large areas of the board. You then segment your ground plane to create a bypass hierarchy and you keep noise generators will separated, impedance wise, from sensitive noise receptors. This is DC. There is a different strategy for AC ground.

 

Before we get too carried away at this point it would be worthwhile to ask what chips are you using and at what frequency are the chips operating? These will have a direct impact on what you are attempting to do.

 

And what do you do on PICs where the Vdd and Vss pins are usually in the middle of the IC not at the end?

 

I'll chime in and agree that Fig. 4 is the best way if the capacitor is connected to a ground plane, since that gives the minimum series parasitic inductance between the power trace currents and the capacitor to ground. It's that series inductance that reduces the effectiveness of a capacitor at high frequencies.

 

4 is right. Feed the power supply to the cap, and then feed the chip power from the cap. A ground plane is a fine thing to have, if you can arrange it.

The PIC processors I've used recently have +V on pin 1, and Gnd on pin 20 (and it's a 20-pin IC), so it's very easy to get the capacitor close to the supply pins. But with supply pins in the middle, the same rule would apply: get the cap close to the chip, and feed the supply to the cap, not to the IC pins. However, given the number of times I've failed to follow this policy and not suffered too badly, I'm sure that it's usually not vital.

 

Large chips like LQFP packages have power pins and groud pins next to each other all around the chip, so blocking gets much more adequate.

 

Before we get too carried away at this point it would be worthwhile to ask what chips are you using and at what frequency are the chips operating? These will have a direct impact on what you are attempting to do.

This is a simple Game show circuit
http://forum.allaboutcircuits.com/showthread.php?t=82641

It is based on CD4000 series logic ICs (1-Quad Dual Input AND gate,2-CD4013 Dual D-type Flop Flops and 1-Dual Quad Input AND gate), 99.99% of the time, the circuit will be in statis; it will only change when 1 or more people press a pushbutton (or the operator reset's the circuit), so frequency is not an issue. I didn't refer to the thread earlier, because I was trying to learn best practices in general - which your comments have helped with. So get carried away!

I do have one place where the power trace (.060") goes first to the power pin and then to the capacitor on CD4013b (which is immediately beside the pin; I thought in this situation, I could get away with this exception.)

I do have attached a current schematic and layout - if that would help.

 

You could use a SIP resistor network instead of those 4k7 resistors on the left and shrink the board a bit in both dimensions, but other than that it looks ok.

 

Thanks for providing this info.

Current drain and signal transitions have the greatest impact on power supply noise. CMOS logic require very little current and do not create a serious noise problem. Also, because the switching threshold for CMOS gates is the midpoint between VDD and VSS, they have greater noise immunity compared with other types of logic.

Where you can anticipate problems is when the LEDs switch state.

To minimize power supply noise when the LEDs switch you should have one 10μF electrolytic capacitor on your logic board and another 10μF cap on the LED display board. Your 47μF cap is ok too.

Nevertheless, it is sound design practice to install 0.1μF capacitors at every logic IC as you have done. The PCB layout in this case is not critical.

 

And what do you do on PICs where the Vdd and Vss pins are usually in the middle of the IC not at the end?

That's when chip capacitors on the bottom of the board are really nice!

If I'm socketing a part like that, I often find that I can install chip caps on the same side of the board underneath the socket.

I remember that you used to be able to find DIP sockets that already had a bypass capacitor between the power pins -- of course you had better make sure that the part you are using it with really does use those pins for power!

 

@Kubeek : I wasn't aware of the SIP part, but you're right - it would have simplified things for me. If I can;t find one locally, next time it is.

@MrChips : The display board was intended to be a passive mounting board for the LEDs. As such, there really is no ground available on it. So where would I mount to 10μF capacitor? My thoughts are on the main logic board, where the Vcc trace passes through the 390Ω resistor and goes to the anode of all LEDs. Or shuld I run ground to the mounting board and include a second capacitor there as well?

 

Worrying too much over this is going on the verge of overkill.
The 47μF cap should be sufficient.

Your LEDs are powered at J2 pin-6. If you wish you could add a 10μF from pin-6 to GND.

Why are you using a common anode resistor R10, 390Ω? You should have a separate series resistor for each LED instead of a single R10.

 

Speaking to the overkill aspect, what you want to shoot for is a compromise approach that works for the majority of the designs you do and that you use as a starting point. For most of your designs you will simply use it out of the box and life will be good. The result will be something that uses more compnents and takes up more space and provides better noise performance than you will need for most of your designs. But what you save in design time will generally offset it. If you need more noise suppression/isolation, you tweak it one way. If you need lower cost/complexity/space you tweak it the other way. This compromise approach may or may not work well for you depending on the type of designs you do.