Would this be anything to do with it?Timing mode sample rate: 1KHz to 500MHz (uses internal clock)
State mode sample rate: 0 to 200MHz (clock provided by circuit under test)
Would this be anything to do with it?Timing mode sample rate: 1KHz to 500MHz (uses internal clock)
State mode sample rate: 0 to 200MHz (clock provided by circuit under test)
Would this be anything to do with it?
So how am I supposed to use it at 500MHz ?Ahhh. That could be it.
B. MorseThe LogicPort will simultaneously sample all 34 channels with full buffer depth at 500MHz in timing mode, 200MHz in state mode.
Sample Mode SetupTiming Mode (Internal Sample Clock)
When timing mode is chosen, the LogicPort will sample at a rate specified using one of the configurable controls on the Waveforms tab.
State Mode (External Sample Clock)
When state mode is chosen, you can select which clock input will be used for sampling, which edge of the clock should be used, and what timing relationship exists between the chosen clock edge and the data you wish to sample. You can also enable qualified sampling to allow the clock input to be qualified by another signal.
LOL, good point... I will do that nowGosh guys, I bet if you posed this question to Intronix, they'd have an answer real real fast - in English even. We're not talking about one of those unsupported Chinese mystery products here. Just a thought...
2 samples? How do you figure? It is showing a little over 4us time period, and at 500MHz sample rate, each sample is 2ns. So, 4us/2ns = ~2K samples. The screen shot says it captured 2.04K samples. Makes sense to me.I'm using CamStudio, it's free...
Actually I just found that if I Zoom a lot, then I actually see something... but i's only 2 samples
I think that's right.I think i'm starting to understand what is going on now...
So, because at 500MHz there is no compression, then I basically see raw samples in the full buffer. And since the frequency that I'm measuring is very small (130Hz), then it basically captured only one state (the High bit).
I saw an option that said something about showing only transitions in the state list. Probably you have that turned on.Before I said 2 samples because that's what it shows in the "State List" tab...
So, now that I understand what is going on... it probably still does some kind of compression on the software side, and since it's the same data from the beginning to end, it shows only the first and last sample, right ? but when I saved it in the CSV file, then it shows all the samples in raw format.
Not at all. You just need to use it for its intended purpose (which is not capturing 130Hz data at a 500MHz sample rate - kinda of pointless). I think you may have a misconception about what a logic analyzer does. It's not a data logger. You need to use appropriate trigger setups to be sure you capture "the right" data.But this kinda sucks, because this makes the 500MHz sample rate almost unusable.
Yup, that's exactly how logic analyzers work. Capture as much as they can, then stop and display. Been that way since the beginning of time (standalone units do the same, except all in one box).This means that it records (samples) until the buffer is full with basically the same data (and it's quite small buffer), then does not sample anything until the data gets sent to the computer. So in the end it will make Huge gaps between buffers received.
If you're worried about gaps between buffers full, then you're still thinking data logger. The gaps between buffers are not very meaningful in logic analysis. It's the data you -do- capture that matters, and capturing the real data of interest depends upon good trigger setups - not chance. When used properly, a logic analyzer can wait virtually forever looking for the trigger event in real-time (yes, even at 500MHz). Then when the trigger event finally occurs, it springs into action and captures some data. A gap of even minutes or hours before/after the data is captured doesn't matter because you've trigger on and captured the meaningful event.But when compression is enabled, then it records more data, therefore the gaps are smaller between the buffers.
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