Parasitic capacitance

Discussion in 'Homework Help' started by prescott2006, Apr 2, 2011.

  1. prescott2006

    Thread Starter Active Member

    Nov 8, 2008
    I am designing a square root circuit by using Mentor Graphic software. As can seen from the attached figure, I want to ask why is the lower waveform is smoother than the upper waveform? The upper waveform is pre-simulation result and lower waveform is after layout has been interconnect. Don't the parasitic capacitance should deteriorate the waveform?:confused: