Dear friends,
i need some urgent help, I am doing a project on power mosfets and the main aim of the project is to see he survival time depending on drain source voltage.Till now i have worked with single mosfet so see how much the maxium energy is driven to the mosfet so that the mosfet gets damaged.

Now my Task is:

I would like to perform paralleling of mosfets, so i have few questions like..

Why do we need to connect two mosfets in parallel?
Is it necessary to measure the individual currents of each mosfet?

Could anyone please responsd as early as possible.

Thank you

 

You are trying to break them or you want to avoid it?

Being able to parallel MOSFETS is one of the advantages they have over BJT's, its standard practice when larger currents need to be switched.

I am not sure what you are asking.

 

Thank you for the reply, i felt the sentence you mentioned is incomplete--when largare currents need to be switched so what happens if we connect them in parallel..

I want to break my mosfet and see the critical energy level at the failure point...i want to know is it necessary to measure individual current?

 

Thank you for the reply, i felt the sentence you mentioned is incomplete--when largare currents need to be switched so what happens if we connect them in parallel..

I want to break my mosfet and see the critical energy level at the failure point...i want to know is it necessary to measure individual current?

Usually not. Since your circuit will be designed with a safety margin AND the layout will assure proper current sharing you don't need to measure individual MOSFET currents.

 

I want to break my mosfet and see the critical energy level at the failure point...

That is what data sheets are for and even if you want to do your own destructive tests for some reason you are going to have to look at much more than just energy.

First of all you need to design a test circuit that will plot the performance of a device. It would need to measure multiple parameters, electrical and physical whilst subjecting the device to a range of tests.

Without this you cant know if the device ids performing within normal parameters so you cant know if you have damaged it.

Assuming you have or can build the above then you will need to program it to apply potentially damaging currents or voltages for specific times and at specific temperatures, then you need to run a full battery of benchmark tests again.

I guess it might make an interesting project but manufactures spend vast quantities of time and money doing this and it isn't likely that you will do it better.

Still confused about what you want to do, exactly.

 

I've seen this done commercially and the only reason I can think of is to lower the D-S resistances when on...for example if the D-S on resistance is 6 ohms, putting 6 Mosfets in parallel will be 1 ohm...a figure that may be significant where source resistances may be an issue.

Cheers, DPW, Everything has limitations...and I hate limitations.

 

I think maybe the OP is asking for verification that MOSFETS in parallel share current equally. The answer is yes. As someone said, that is one of the big benefits of using MOSFETs in high current situations. You can parallel them and they will share the current.

The reason this works is that the on-resistance of the MOSFET is a positive function of temperature. So if one of your MOSFETS has a lower on-resistance than the others, and therefore draws more current, it heats up and increases its on-resistance, thus decreasing its current draw. The result is that the MOSFETs current balance.

 

I think maybe the OP is asking for verification that MOSFETS in parallel share current equally. The answer is yes. As someone said, that is one of the big benefits of using MOSFETs in high current situations. You can parallel them and they will share the current.

The reason this works is that the on-resistance of the MOSFET is a positive function of temperature. So if one of your MOSFETS has a lower on-resistance than the others, and therefore draws more current, it heats up and increases its on-resistance, thus decreasing its current draw. The result is that the MOSFETs current balance.

For the balancing to occur it's important that the MOSFETs stay at close to the same temperature, with the only difference being due to the difference in on-resistance between them. Thus they should all be mounted on the same heatsink.

 

Thank you so much for all your kind replies.

 

In the above post one of our collague has told he is still confused what am i doing in my project, here is my explanation:
The main aim of my project is to build a test setup fo calculating the robustness of different type of power mosfets in linear mode.
I have build a simple test setup with inductance, power supply, power mosfet and clamping diodes.
I have done few test for different mosfets by applying multiple pulses to each mosfet until failure at both room temperature and high temperature using different loads.
The purpose of doing this was to see how much energy the mosfet could take, so that we can be below the critical pioint..
The whole above test was done for one power mosfet each time and i obsevered that the failure of mosfet and high temperature was early compared to room temperature.
Now i am finished with working with single mosfet..
Now i have to do paralleling of mosfets.
My question was do i need to measure individual currents..If i have to do that then i need to change my test setup.
What would be the difference if i mesaure individual currents or over all current..

 

I need an urgent help , i am doing paralling of mosfets and i am measuring individual currents in each mosfet. previously i have done test for individual mosfet and i have applied gate pulse of 10v to switch on my mosfet as now i am connecting two mosfets do i need to double my gate pulse to switch on my mosfet ?

 

The gate of a Mosfet uses no DC current. But it is a fairly high value capacitor that needs plenty of current to charge and discharge quickly.
Two Mosfets have twice as much capacitance as one so the charge and discharge currents must be doubled when the Mosfets are paralleled.

Why do your testing? A name-brand manufacturer guarantees that their product perform as shown in their datasheets.
Are you looking at fake counterfeit Mosfets?
Or are you looking at Mosfets produced by an unknown manufacturer who cannot be trusted?

 

I was wondering the same thing ... why perform this tesing? If its for academic purposes, then great! But if you've been seeing MOSFET failures in actual products and are thinking you will characterize MOSFETs to see which will survive better ... then I believe you're heading in the wrong direction.

Modern MOSFETs are quite robust and will rarely fail if designed properly and used within their specifications. Here are some things to look at in your designs ...

(1) Temperature. How hot are you running the parts. Consider temperature rise + worst case and ambient temperature. Measure it!

(2) Drain voltage. Use a good quality (fast) scope and look at the edges of the switching waveforms on your MOSFETs. Are there narrow spikes that are exceeding the MOSFET drain voltage rating? Maybe you need a snubber.

(3) Does your circuit have the possibility of having two MOSFETs on at the same time resulting in excessively large currents, such as an H-bridge? Again, look at the waveforms with a scope and make sure that both FETs are never on at the same time.

(4) Look at the gate drive signal with a scope. Is it exceeding the gate voltage rating, either positive or negative? Is there excessive ringing and overshoot that is possibly exceeding the part rating? Good PCB layout of the gate drive can be very important to get a nice clean signal.

(5) Maybe your gate drive circuit does not have enough current drive capability to charge up the MOSFET gate capacitance quickly. A slow transition on the gate means the MOSFET stays in its active region longer than necessary during a switching transition. In this case the MOSFET will dissipate more power than you expected.

(6) Thinking about #2 above ... is your MOSFET switching an inductive load? Perhaps you're getting a bunch of ringing and/or overshoot that is exceeding the part rating.

Basically, design the circuit well, check all the waveforms carefully, make sure the device is operating within specs, and it will not fail.

Oh, one more very, very, very important thing that can be easy to miss ...

(7) Consider the startup case. Make sure that the MOSFET is turned off until you are ready to turn it on. For example, if you had a micro-controller that switched N-channel MOSFETs, and you did not use a pull-down resistor to hold the gates low, the gates might float high and turn on the MOSFETs during the time when your micro-controler was booting and then code was setting up the output pins.

 

Here are a couple of really good app notes:
http://www.irf.com/technical-info/appnotes/an-941.pdf
http://www.irf.com/technical-info/appnotes/para.pdf

 

@Audioguru,JMac3108: Thank you so much for your kind suggestions, i would follow this and update you about the working soon!!!

 

I have earlier tested with few superjunction, trench, vishay type of mosfets and now i would like to compare the following:
Comparsion of transistor technologies(Superjunction Vs Trench)?
comparsion of implementations?(Superjunction Fets Vs Infenion Vs ST )

It would really be very kind if you could explain me what paraments do we need to consider for this comparsion especially implementations?