Parallel to Serial Converter

Discussion in 'Homework Help' started by rishid, Jul 16, 2006.

  1. rishid

    Thread Starter New Member

    Oct 24, 2005
    8
    0
    Hi,

    Just designing a simple PISO logic design. I already built it and is working fine just need a little help on making it work continously.

    Inputs:
    pardata[7:0]
    dataready
    clock

    Outputs:
    serout
    ready

    Basically 'ready' becomes 1 when it is ready to accept new data, this is done by just a ripple counter counting out 8 bits. Dataready controls whether or not to load parallel data or serialize data.

    Problem I have, cannot figure out how to get 'dataready' to become 1 when 'ready' becomes 1. Can I just wire 'ready' to 'dataready'?

    Thanks,

    RishiD
     
  2. windoze killa

    AAC Fanatic!

    Feb 23, 2006
    605
    24
    Not having the actual circuit I can't answer for sure. But you should be able to connect them directly or to be safe pass it through a non-inverting buffer or 2 inverting buffers.
     
  3. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    143
    The only problem with using buffers is that they will introduce a delta-time-delay between "ready" going high and "dataready" going high due to the gates. This can obviously be a problem if the clock-rate is faster than delta.

    Likewise, although not seeing the circuit, I would say that it is safe to directly connect "ready" to "dataready" for your purposes. I assume you are designing the PISO using a hardware description language and plan to programme the design to a PAL or something similar?

    Dave
     
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    I think ready and dataready are two different signals to control two different events. My understanding is, dataready is there to signal the PISO that the input data at the parallel input is valid and serialisation can begin. Ready, on the other hand, signals that the serialisation has been completed and the PISO is available to receive next parallel data.

    Consider this scenario, one byte of parallel data was serialised and the ready signal was asserted. If there wasn't any new data available at the PISO input, then dataready shouldn't be asserted. However, if dataready was connected to ready signal, then it would be asserted, without any valid data at the PISO input. This is an error.

    What you should do is to check whether the data is available, then assert dataready when the ready signal is asserted.

    Edit: typo correction.
     
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