parallel-series-parallel register troubleshooting

Discussion in 'Homework Help' started by justtrying, Mar 14, 2011.

  1. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    I am trying to troubleshoot a system with registers that supposed to go parallel in - series out and then series-in parallel-out. I believe that I have the concept right with D-latches, using clock and enable gates to load and unload each latch in sequence but when I run it on multisim my parallel outputs do not correspond to the inputs in any way. I have not been able to figure out what the problem is. Am I misundeerstanding something? Any input is welcome.
     
  2. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    don't mean to be impatient, but wondering why there is no input at all, was really hoping to get some help here. Digital is really killing me along with any potential for success, a bit depressing really, 0011...:confused:
     
  3. guitarguy12387

    Active Member

    Apr 10, 2008
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    You gotta give more info about your problem. What is this trying to do?

    Also, look into shift registers
     
  4. guitarguy12387

    Active Member

    Apr 10, 2008
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    Also, that diagram could use some labels and stuff.
     
  5. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    the diagram has some lables on it but I had to remove others because of poor pdf quality. I have looked into shift registers. As per my understanding, the first pair of latches (I am sorry for missing lables, but I have never posted jpeg or pdf files before) is supposed to work like this: first latch is loaded with data that is transmitted when enable (oc) is low and clock is applied. The data can then be transmitted to second latch in series as another clock is applied. For 4 bits of data 4 clocks will be necessary. This is shift register, right?

    The last pair supposed to take incoming serial data and provide parallel output. So first latch is loaded with 4 bits of serial data as 4 clocks are applied, data should then appear on parallel outputs at which point the second latch can be enabled to transmit the data in parallel.

    Do I have the idea right or not? I will try to post a better diagram, but I may not have the time to work it out right now, I need to understand the concept more than anything else, like I said, all help is appreciated...
     
  6. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    better diagram, maybe?
     
    Last edited: Mar 17, 2011
  7. guitarguy12387

    Active Member

    Apr 10, 2008
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    Greetings,

    Are you simply trying to add 4 unit delays or something? What is the point of going parallel-to-serial -> serial-to-parallel? ... it's already in parallel haha!

    Also, i'm kinda scared by those feedback loops around the DFFs. You have two FFs driving one node. Thats not good.

    What is the application of this circuit? What's it do?
     
  8. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    ultimately the parallel outputs of the last FF go into a 74LS47 to drive a 7 segment LED. I don't think it is a practical circuit, it is just a lab to drive one nuts... I'm sorry to sound so frastrated. I think the parallel-serial part is OK. I am not sure whether the serial-parallel is correct though. The circuit didn't work in the lab, but I probably didn't wire it correctly, the teacher refuses to help and there is no open lab. So I am trying to make it work on multisim but it only gives the right output for an input of 1010, of course I could be screwing up the enabling etc.

    Thanks for looking at it,
    still scratching my head though

    For 2 FF driving one node, are you referring to U2 and U4? The way I understood it, this is OK because when one is enabled, the other is disabled. But than again, I have been doing digital for 2 months with minimal instruction...
     
  9. guitarguy12387

    Active Member

    Apr 10, 2008
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    Haha okay. Oh, the things we do in the name of education haha!

    No, i mean the output of U1 and U2 both drive the nodes near the wire labeled '1'.

    Ohhh i didn't have a close enough look at your enable circuits

    Don't worry, i'd be frustrated too... its one seriously messed up circuit haha.

    What are you allowed to change? Can you give the exact problem description? I just don't see how that circuit is going to do anything you want it to. I can kinda, sorta see what you're trying to do... but i don't think its going to work. You really can't use feedback in that way in digital circuits. If one thing drives the node high while the other is driving low, you'll get a short. If you're married to the serial -> parallel business (not sure what your requirements are), you probably just want to look up schematics for series to parallel and parallel to series shift registers and use them directly.
     
  10. justtrying

    Thread Starter Active Member

    Mar 9, 2011
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    we were supposed to make a parallel in - serial out shift register and a serial in - parallel out shift register and then interconnect the registers to drive the display. It is actually even worse because there are 8 inputs. We were supposed to use the enable to control data transfer.
     
  11. djsfantasi

    AAC Fanatic!

    Apr 11, 2010
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