Hi!
I was studying the propagation time of inverter CMOS. The text where I study considers only the gate capacitors and the drain capacitors of the NMOS and PMOS. This is schema:
The objective is calculate CL capacitors. The text says that the CL is in parallel with CDB,n ok because V3 = V2 = Vout - 0. Very well. Then it says that CDW,p is in parallel with CL. Why ?? For me V1 = Vdd-Vout and V3 = Vout - 0. Vdd = 1V. I don't understand because the CL is in parallel with CDW,p. Help me please.
I was studying the propagation time of inverter CMOS. The text where I study considers only the gate capacitors and the drain capacitors of the NMOS and PMOS. This is schema:
The objective is calculate CL capacitors. The text says that the CL is in parallel with CDB,n ok because V3 = V2 = Vout - 0. Very well. Then it says that CDW,p is in parallel with CL. Why ?? For me V1 = Vdd-Vout and V3 = Vout - 0. Vdd = 1V. I don't understand because the CL is in parallel with CDW,p. Help me please.