P89LPC922 blinking LED help

Discussion in 'Embedded Systems and Microcontrollers' started by greenbreen, Dec 19, 2010.

  1. greenbreen

    Thread Starter New Member

    Dec 19, 2010
    2
    0
    Hello,

    I'm new to the 80C51 family of microcontrollers, although I have worked with PIC18F microcontrollers a long time ago. I'm trying to get started with the P89LPC922 in a 20-pin DIP package. I'm just trying to get a "Hello World" type project up and running. The system should blink and LED on and off at a rate detectable to a human. I wired up the hardware, wrote the firmware and programmed the device, but it doesn't seem to do anything.

    I have 3.6V on pins 4 (active low reset) and 15 (VDD), and I have ground on pin 5 (VSS). I'm using pin 2 (P1.7) to blink the light. All other pins are not connected. If I disconnect from the microcontroller and apply 3.6V directly to the LED, it lights with less than 10mA of current used.

    Below is the C code I used for the firmware. The header file just gives the locations of the SFRs. I'll post it if anyone wants to see it. I compiled the source down to an intel hex file with SDCC.
    Code ( (Unknown Language)):
    1.  
    2. #include <P89LPC922.h>
    3.  
    4. void main()
    5. {
    6.     long i;
    7.  
    8.     // Configure Port 1 bit 7 in push-pull output mode
    9.     P1M1 = 1;
    10.     P1M2 = 0;
    11.  
    12.     P1_7 = 1;   // Turn on LED
    13.     while(1) // Main loop
    14.     {
    15.         for(i=1;i<100000;i++);  // Delay so human can see
    16.         P1_7 = !P1_7;  // Toggle LED
    17.     }
    18. }
    19.  
    I programmed the microcontroller with a Galep-5 universal programmer. The programmer reports that programming is successful. The configuration byte is 0x63, which disables the watchdog timer and selects the internal RC oscillator, among other things.

    When power is applied, the LED remains off. I have 3.6V on pins 4 and 15 and 0V on pin 5. The other pins including pin 2 seem to stay around 0.3V, but they wander, sometimes a high as a volt. I'm not sure what do try next.
     
  2. greenbreen

    Thread Starter New Member

    Dec 19, 2010
    2
    0
    Hello,

    I found a solution at http://forum.best-microcontroller-projects.com/viewtopic.php?f=5&t=2060&p=2773#p2773

    In case that website ever becomes unavailable, I'll re-post the answer here.

    Hi, Kev. Thanks for your reply. You got it! I made a couple of mistakes. As you pointed out, I have P1M1 and P1M2 backwards. Also, in my C code the lines
    Code ( (Unknown Language)):
    1.  
    2.    P1M1 = 1;
    3.    P1M2 = 0;
    4.  
    set all the P1M2 bits to 0, but only sets bit 0 of P1M1 to 1, not what I intended. I found a nice website, http://www.codearchitect.org, that generates C code for the P89LPC922, among other microcontrollers, that would have prevented this mistake. I changed the code above to
    Code ( (Unknown Language)):
    1.  
    2.   P1M1 &= 0x7F;
    3.   P1M2 |= 0x80;
    4.  
    , which the codearchitect website suggested.

    For anyone else that may be having trouble getting started with this microcontroller, here are a few other things I found. The default behavior of this chip is to start executing code at the boot ROM vector rather than 0x0000. It turns out that my programmer was changing that configuration so that it would start executing at 0x0000, but someone with a different programming method might have this problem. I also tried putting 15uF capacitors between my power and ground rails. It didn't make a difference with my power supply and circuit, but I've seen this technique solve strange circuit problems in the past. I'm also posting the header file, P89LPC922.h, below, so that anyone looking for help and running across this thread will have a complete solution to getting up and running with the P89LPC922:
    Code ( (Unknown Language)):
    1.  
    2. /*------------------------------------------------------------------//--------
    3. P89LPC922.H
    4. (English)
    5. This header allows to use the microcontroler Philips P89LPC922
    6. with the compiler SDCC.
    7.  
    8. Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
    9.  
    10.    This library is free software; you can redistribute it and/or
    11.    modify it under the terms of the GNU Lesser General Public
    12.    License as published by the Free Software Foundation; either
    13.    version 2.1 of the License, or (at your option) any later version.
    14.  
    15.    This library is distributed in the hope that it will be useful,
    16.    but WITHOUT ANY WARRANTY; without even the implied warranty of
    17.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    18.    Lesser General Public License for more details.
    19.  
    20.    You should have received a copy of the GNU Lesser General Public
    21.    License along with this library; if not, write to the Free Software
    22.    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
    23.  
    24. (Spanish-Espa?ol)
    25. Archivo encabezador para el ucontrolador Philips P89LPC922.
    26. Derechos de copy (DC) 2005.  OMAR ESPINOSA P.  E-mail: opiedrahita2003 AT yahoo.com
    27. Uso libre
    28. //------------------------------------------------------------------//--//------*/
    29. #ifndef __REG922_H__
    30. #define __REG922_H__
    31.  
    32. //*  BYTE Registers  *//
    33. __sfr __at (0x80) P0     ;
    34. __sfr __at (0x90) P1     ;
    35. __sfr __at (0xB0) P3     ;
    36. __sfr __at (0xD0) PSW    ;
    37. __sfr __at (0xE0) ACC    ;
    38. __sfr __at (0xF0) B      ;
    39. __sfr __at (0x81) SP     ;
    40. __sfr __at (0x82) DPL    ;
    41. __sfr __at (0x83) DPH    ;
    42. __sfr __at (0x87) PCON   ;
    43. __sfr __at (0x88) TCON   ;
    44. __sfr __at (0x89) TMOD   ;
    45. __sfr __at (0x8A) TL0    ;
    46. __sfr __at (0x8B) TL1    ;
    47. __sfr __at (0x8C) TH0    ;
    48. __sfr __at (0x8D) TH1    ;
    49. __sfr __at (0xA8) IEN0   ;
    50. __sfr __at (0xB8) IP0    ;
    51. __sfr __at (0x98) SCON   ;
    52. __sfr __at (0x99) SBUF   ;
    53.  
    54.  
    55. __sfr __at (0xA2) AUXR1  ;
    56. __sfr __at (0xA9) SADDR  ;
    57. __sfr __at (0xB9) SADEN  ;
    58. __sfr __at (0xBE) BRGR0  ;
    59. __sfr __at (0xBF) BRGR1  ;
    60. __sfr __at (0xBD) BRGCON ;
    61. __sfr __at (0xAC) CMP1   ;
    62. __sfr __at (0xAD) CMP2   ;
    63. __sfr __at (0x95) DIVM   ;
    64. __sfr __at (0xE7) FMADRH ;
    65. __sfr __at (0xE6) FMADRL ;
    66. __sfr __at (0xE4) FMCON  ;
    67. __sfr __at (0xE5) FMDATA ;
    68. __sfr __at (0xDB) I2ADR  ;
    69. __sfr __at (0xD8) I2CON  ;
    70. __sfr __at (0xDA) I2DAT  ;
    71. __sfr __at (0xDD) I2SCLH ;
    72. __sfr __at (0xDC) I2SCLL ;
    73. __sfr __at (0xD9) I2STAT ;
    74. __sfr __at (0xF8) IP1    ;
    75. __sfr __at (0xF7) IP1H   ;
    76. __sfr __at (0x94) KBCON  ;
    77. __sfr __at (0x86) KBMASK ;
    78. __sfr __at (0x93) KBPATN ;
    79. __sfr __at (0x84) P0M1   ;
    80. __sfr __at (0x85) P0M2   ;
    81. __sfr __at (0x91) P1M1   ;
    82. __sfr __at (0x92) P1M2   ;
    83. __sfr __at (0xB1) P3M1   ;
    84. __sfr __at (0xB2) P3M2   ;
    85. __sfr __at (0xB5) PCONA  ;
    86. __sfr __at (0xF6) PT0AD  ;
    87. __sfr __at (0xDF) RSTSRC ;
    88. __sfr __at (0xD1) RTCCON ;
    89. __sfr __at (0xD2) RTCH   ;
    90. __sfr __at (0xD3) RTCL   ;
    91. __sfr __at (0xBA) SSTAT  ;
    92. __sfr __at (0x8F) TAMOD  ;
    93. __sfr __at (0x96) TRIM   ;
    94. __sfr __at (0xA7) WDCON  ;
    95. __sfr __at (0xC1) WDL    ;
    96. __sfr __at (0xC2) WFEED1 ;
    97. __sfr __at (0xC3) WFEED2 ;
    98. __sfr __at (0xB7) IP0H   ;
    99. __sfr __at (0xE8) IEN1   ;
    100.  
    101. /*  BIT Registers  */
    102. /*  PSW   */
    103. __sbit __at (0xD0) PSW_0   ;
    104. __sbit __at (0xD1) PSW_1   ;
    105. __sbit __at (0xD2) PSW_2   ;
    106. __sbit __at (0xD3) PSW_3   ;
    107. __sbit __at (0xD4) PSW_4   ;
    108. __sbit __at (0xD5) PSW_5   ;
    109. __sbit __at (0xD6) PSW_6   ;
    110. __sbit __at (0xD7) PSW_7   ;
    111.  
    112. #define CY    PSW_7
    113. #define AC    PSW_6
    114. #define F0    PSW_5
    115. #define RS1   PSW_4
    116. #define RS0   PSW_3
    117. #define OV    PSW_2
    118. #define F1    PSW_1
    119. #define P     PSW_0
    120.  
    121. /*  TCON  */
    122. __sbit __at (0x8F) TCON_7  ;
    123. __sbit __at (0x8E) TCON_6  ;
    124. __sbit __at (0x8D) TCON_5  ;
    125. __sbit __at (0x8C) TCON_4  ;
    126. __sbit __at (0x8B) TCON_3  ;
    127. __sbit __at (0x8A) TCON_2  ;
    128. __sbit __at (0x89) TCON_1  ;
    129. __sbit __at (0x88) TCON_0  ;
    130.  
    131. #define TF1   TCON_7
    132. #define TR1   TCON_6
    133. #define TF0   TCON_5
    134. #define TR0   TCON_4
    135. #define IE1   TCON_3
    136. #define IT1   TCON_2
    137. #define IE0   TCON_1
    138. #define IT0   TCON_0
    139.  
    140. /*  IEN0   */
    141. __sbit __at (0xAF) IEN0_7  ;
    142. __sbit __at (0xAE) IEN0_6  ;
    143. __sbit __at (0xAD) IEN0_5  ;
    144. __sbit __at (0xAC) IEN0_4  ;
    145. __sbit __at (0xAB) IEN0_3  ;
    146. __sbit __at (0xAA) IEN0_2  ;
    147. __sbit __at (0xA9) IEN0_1  ;
    148. __sbit __at (0xA8) IEN0_0  ;
    149.  
    150. #define EA    IEN0_7
    151. #define EWDRT IEN0_6
    152. #define EBO   IEN0_5
    153. #define ES    IEN0_4    // alternatively "ESR"
    154. #define ESR   IEN0_4
    155. #define ET1   IEN0_3
    156. #define EX1   IEN0_2
    157. #define ET0   IEN0_1
    158. #define EX0   IEN0_0
    159.  
    160. /*  IEN1   */
    161. __sbit __at (0xEA) IEN1_2  ;
    162. __sbit __at (0xE9) IEN1_1  ;
    163. __sbit __at (0xE8) IEN1_0  ;
    164.  
    165. #define EC    IEN1_2
    166. #define EKBI  IEN1_1
    167. #define EI2C  IEN1_0
    168.  
    169. /*  IP1   */
    170. __sbit __at (0xFE) IP1_6   ;
    171. __sbit __at (0xFA) IP1_2   ;
    172. __sbit __at (0xF9) IP1_1   ;
    173. __sbit __at (0xF8) IP1_0   ;
    174.  
    175. #define PST   IP1_6
    176. #define PC    IP1_2
    177. #define PKBI  IP1_1
    178. #define PI2C  IP1_0
    179.  
    180. /*  IP0   */
    181. __sbit __at (0xBE) IP0_6   ;
    182. __sbit __at (0xBD) IP0_5   ;
    183. __sbit __at (0xBC) IP0_4   ; // alternatively "PSR"
    184. __sbit __at (0xBB) IP0_3   ;
    185. __sbit __at (0xBA) IP0_2   ;
    186. __sbit __at (0xB9) IP0_1   ;
    187. __sbit __at (0xB8) IP0_0   ;
    188.  
    189. #define PWDRT IP0_6
    190. #define PBO   IP0_5
    191. #define PS    IP0_4      // alternatively "PSR"
    192. #define PSR   IP0_4
    193. #define PT1   IP0_3
    194. #define PX1   IP0_2
    195. #define PT0   IP0_1
    196. #define PX0   IP0_0
    197.  
    198. /*  SCON  */
    199. __sbit __at (0x98) SCON_0  ;
    200. __sbit __at (0x99) SCON_1  ;
    201. __sbit __at (0x9A) SCON_2  ;
    202. __sbit __at (0x9B) SCON_3  ;
    203. __sbit __at (0x9C) SCON_4  ;
    204. __sbit __at (0x9D) SCON_5  ;
    205. __sbit __at (0x9E) SCON_6  ;
    206. __sbit __at (0x9F) SCON_7  ;
    207.  
    208. #define SM0   SCON_7  // alternatively "FE"
    209. #define FE    SCON_7
    210. #define SM1   SCON_6
    211. #define SM2   SCON_5
    212. #define REN   SCON_4
    213. #define TB8   SCON_3
    214. #define RB8   SCON_2
    215. #define TI    SCON_1
    216. #define RI    SCON_0
    217.  
    218. /*  I2CON  */
    219. __sbit __at (0xDE) I2CON_6 ;
    220. __sbit __at (0xDD) I2CON_5 ;
    221. __sbit __at (0xDC) I2CON_4 ;
    222. __sbit __at (0xDB) I2CON_3 ;
    223. __sbit __at (0xDA) I2CON_2 ;
    224. __sbit __at (0xD8) I2CON_0 ;
    225.  
    226. #define I2EN  I2CON_6
    227. #define STA   I2CON_5
    228. #define STO   I2CON_4
    229. #define SI    I2CON_3
    230. #define AA    I2CON_2
    231. #define CRSEL I2CON_0
    232.  
    233. /*  P0    */
    234. __sbit __at (0x80) P0_0    ;
    235. __sbit __at (0x81) P0_1    ;
    236. __sbit __at (0x82) P0_2    ;
    237. __sbit __at (0x83) P0_3    ;
    238. __sbit __at (0x84) P0_4    ;
    239. __sbit __at (0x85) P0_5    ;
    240. __sbit __at (0x86) P0_6    ;
    241. __sbit __at (0x87) P0_7    ;
    242.  
    243. #define KB7   P0_7   // alternatively "T1"
    244. #define T1    P0_7
    245. #define KB6   P0_6   // alternatively "CMP1"
    246. #define CMP1  P0_6
    247. #define KB5   P0_5
    248. #define KB4   P0_4
    249. #define KB3   P0_3
    250. #define KB2   P0_2
    251. #define KB1   P0_1
    252. #define KB0   P0_0   // alternatively "CMP2"
    253. #define CMP2  P0_0
    254.  
    255. /*  P1  */
    256. __sbit __at (0x90) P1_0    ;
    257. __sbit __at (0x91) P1_1    ;
    258. __sbit __at (0x92) P1_2    ;
    259. __sbit __at (0x93) P1_3    ;
    260. __sbit __at (0x94) P1_4    ;
    261. __sbit __at (0x95) P1_5    ;
    262. __sbit __at (0x96) P1_6    ;
    263. __sbit __at (0x97) P1_7    ;
    264.  
    265. #define RST   P1_5
    266. #define INT1  P1_4
    267. #define INT0  P1_3   // alternatively "SDA"
    268. #define SDA   P1_3
    269. #define T0    P1_2   // alternatively "SCL"
    270. #define SCL   P1_2
    271. #define RxD   P1_1
    272. #define TxD   P1_0
    273.  
    274. /*  P3  */
    275. __sbit __at (0xB0)  P3_0   ;
    276. __sbit __at (0xB1)  P3_1   ;
    277.  
    278. #define XTAL1 P3_1
    279. #define XTAL2 P3_0
    280.  
    281. #endif
    282.  
    Thanks again, Kev!
     
Loading...