Hi folks,
I am about to start playing with micro controllers to manage some alternative energy projects, just the control not any high voltage stuff.
The first thing that I want to do is manage my battery charging from PV's
I have a 12v system with circa 600W of panels, various ages and types.
I managed to get some p-channel FET's at a great price, low enough to parallel several on each 10A charging circuit thus reducing the effective RDS On they are IRF5305PBF.
I have never used P-Channel FET's although I got some great help here a while back with N-Channel devices for an avr I was struggling with.
Obviously I want, in fact need, to implement a high side switch which will be fed a PWM signal from the uP. It will not need to be particularly fast, but I appreciate that too slow a switching frequency will cause undesirable ripple on the batteries.
I know about totem pole drivers and will probably utilise this topology but having bought the FET's, thinking the driver would be far simpler than a bootstrap needed for N-Channel devices I realised that I hadn't thought it through.
Here is the problem
My PV's could float at anything up to 24v with no load.
VGS Max is -20 with -10 being the figure used to specify RDS ON
I am assuming that I probably don't want to subject the gate to much above -15 with -12 being the target.
When the device is on there isn't a problem, assuming -15 is OK, because the PV voltage will drop to circa 14 but I am worried that when I first pull the gate low, before the device conducts fully, I will be stressing the gate to the point that it will probably damage the device.
Is this correct? and if so is there a simple solution?
Would the solution below work or am I missing the point.
I am assuming that I need a rail that floats at S-12v and that the driver circuit would have to switch G between that and S in the same way as I would need to switch between 0 and 12 in an N-Channel low side circuit.
Am I correct?
If so could I use a zenner / resistor divider to generate this rail and add a cap to provide sufficiently low impedance for the gate drive during the switch transition?
Lastly, how do I calculate the current that my gate drive needs to handle from the gate charge figures and if that is in fact possible would it be symmetrical, charge being the reciprocal of discharge I mean.
I am assuming that the higher the impedance of the gate driver the longer it will take to switch, generating losses and more importantly heat. I am assuming that some amps for some time = some charge but I wouldn't have a clue how to work that out particularly as I suspect that the current in the gate will be inversely proportional the the charge at any given point.
Any help will be appreciated and please don't pull any punches, being wrong is how I learn.
Thanks in advance
Al
I am about to start playing with micro controllers to manage some alternative energy projects, just the control not any high voltage stuff.
The first thing that I want to do is manage my battery charging from PV's
I have a 12v system with circa 600W of panels, various ages and types.
I managed to get some p-channel FET's at a great price, low enough to parallel several on each 10A charging circuit thus reducing the effective RDS On they are IRF5305PBF.
I have never used P-Channel FET's although I got some great help here a while back with N-Channel devices for an avr I was struggling with.
Obviously I want, in fact need, to implement a high side switch which will be fed a PWM signal from the uP. It will not need to be particularly fast, but I appreciate that too slow a switching frequency will cause undesirable ripple on the batteries.
I know about totem pole drivers and will probably utilise this topology but having bought the FET's, thinking the driver would be far simpler than a bootstrap needed for N-Channel devices I realised that I hadn't thought it through.
Here is the problem
My PV's could float at anything up to 24v with no load.
VGS Max is -20 with -10 being the figure used to specify RDS ON
I am assuming that I probably don't want to subject the gate to much above -15 with -12 being the target.
When the device is on there isn't a problem, assuming -15 is OK, because the PV voltage will drop to circa 14 but I am worried that when I first pull the gate low, before the device conducts fully, I will be stressing the gate to the point that it will probably damage the device.
Is this correct? and if so is there a simple solution?
Would the solution below work or am I missing the point.
I am assuming that I need a rail that floats at S-12v and that the driver circuit would have to switch G between that and S in the same way as I would need to switch between 0 and 12 in an N-Channel low side circuit.
Am I correct?
If so could I use a zenner / resistor divider to generate this rail and add a cap to provide sufficiently low impedance for the gate drive during the switch transition?
Lastly, how do I calculate the current that my gate drive needs to handle from the gate charge figures and if that is in fact possible would it be symmetrical, charge being the reciprocal of discharge I mean.
I am assuming that the higher the impedance of the gate driver the longer it will take to switch, generating losses and more importantly heat. I am assuming that some amps for some time = some charge but I wouldn't have a clue how to work that out particularly as I suspect that the current in the gate will be inversely proportional the the charge at any given point.
Any help will be appreciated and please don't pull any punches, being wrong is how I learn.
Thanks in advance
Al