Op amp integrator with reset circuit not working properly

Discussion in 'General Electronics Chat' started by atferrari, Aug 30, 2015.

  1. atferrari

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    Jan 6, 2004
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    Simulation of integrator with reset-to-zero circuit for 2 Vin ramps (-V to +V and viceversa). The "chopping" signal (Vctrl) is used to verify the output at different ranges of Vin.

    Integrator 2 cases & sanity check.png

    For Vin values above 0V, the output gets hard limited (?!). The reason obviously resides on the MOSFET whose source sits on the summing point (always at 0V). A sanity check shows the integrator itself, (no reset circuit), working OK.

    Integrator reset 3 panes.png

    For anyone interested I attached the .asc file plus the subckt file for the NMOS 2N7000 (also used the BS170 with similar results). I stripped out any .INCLUDE or .LIB directive since I am using now full paths to my bag of models and can forget copying models / subckts here and there every time.
     
  2. OBW0549

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    Mar 2, 2015
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    Your hard limiting is caused by the intrinsic source-to-drain body diode in the MOSFET, which conducts whenever the integrator output tries to go below about -0.65 volts.
     
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  3. atferrari

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    Believe me OBW, in the future I will never forget there is an intrinsic diode S-to-D in a MOSFET. A JFET made it.

    Gracias.

    A JFET solved that.png
     
  4. crutschow

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    It looks like the JFET is clamping the negative output above a certain voltage level indicating the JFET shut-off gate voltage is not negative enough..
    The JFET gate voltage must be kept more negative the the maximum op amp negative output plus the worst-case cut-off gate-source voltage of the JFET.

    Alternately you could use a CMOS transmission gate to discharge the capacitor. For that the CMOS power must be the plus and minus voltage, and the control voltage must go between the plus voltage and the minus voltage.
     
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  5. PeterCoxSmith

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    Feb 23, 2015
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    If you don't want to apply a reset signal, for example with a continuous input, then you can use a very high value resistor in place of the fet. It does cause roll off in the performance at higher frequencies but it does mean you do not have the requirement to fire the reset.
     
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  6. atferrari

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    Inf fact I tried to avoid using a CD4066 (which I have handy) because I would use just one gate!

    LTSpice shows that I need around -12V to cut that J310 completely. My circuit uses +/-9V only. Not sure what to do.
     
  7. atferrari

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    The reset would be at random (PID control loop). I tried a diode bridge as well but since I need it reset to zero, I found no other way up to now other than the FET or the CMOS gate, what I am trying to avoid.

    Gracias.
     
  8. crutschow

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    What's wrong with using only one gate of the 4066?
    Are you concerned about PCB circuit area?
    Certainly the 4066 would readily handle a ±9V signal with ±9V supplies.
     
  9. OBW0549

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  10. dl324

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    Voltage doubler?
     
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  11. atferrari

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    Carl, OBW and DL, gracias for posting again.

    Initially I thought in a voltage doubler, later, maybe to resign and use the CD4066 but, after an espresso at the cafeteria, I realized that I was struggling to get an output close to the saturation limits (appr +/- 7V for a TL072) what, considering this is going to be the I component of a PID, is not needed.

    My preliminary LTSpice tests that I completed minutes ago, show that by scaling things down, I could do it well.
    If my workload allows tomorrow, I will test real hardware.

    Being more used to digital things, I conclude, once again, that there is life under 5V after all... :p
     
  12. atferrari

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    To avoid windup I plan to use a window comparator so the integrator is kept at 0 output until called for its duty. Have to test that anyway.
     
  13. PeterCoxSmith

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    Feb 23, 2015
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    The fet or analog switch reset is the classic way to initialise a PID loop to stop the integrator winding up (and down again) at power up. Also you may need to consider applying precision limits to the integrator so that the integral term does not cause the controller to overshoot and require a long period of recovery.
     
  14. atferrari

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    I learnt very recently about controlling the windup problem. As I said, I plan to use the integrator in reset state since start. If nothing better comes, it will be via a window comparator with Vref (setpoint) as the input.

    BTW, I tested already a nice circuit able to set the window's center and span separately.

    I still have no idea:

    How could I pre-estimate/calculate? the window's upper/lower (precision) limits?
    Should they be carved in stone or manually / dinamically adjusted by the process itself?

    Maybe one or two rules of thumb from any of your secret notebooks? :)

    Just in case: I am not confusing this with gain (Ki) term.

    Gracias for your time.
     
  15. PeterCoxSmith

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    Feb 23, 2015
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    You only need to fire the reset at power up to initialise the integrator to zero volts, after that only reset if the power fails. This is a straight forward power up reset function that allows say 10msec for the system to settle before the integrator starts.

    So I'm not sure what your window comparator does?

    The integrator function in a PID loop needs + and - limit so that the output stage is not driven beyond its maximum saturated output. So for example if your controller output is driven full on by a voltage of say 3v, you need to limit the integrator output to + and - 3V. This clamp or clip function can be implemented with zener diodes if you can stand the lack of precision. Or you can implement the integrator with a true rail to rail op amp and set up precision rails using a Vref.
     
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