op amp, capacitive loading, again

Discussion in 'General Electronics Chat' started by bug13, May 24, 2013.

  1. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
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    [​IMG]

    Please refer to the circuit above, when the current through R2 is about 1A, and the V_drain is under 7V, the circuit starts to oscillate.


    but when V_drain > 7V seen to work alright, just under 2mV ripple on the V_source.


    So my question is, what cause it? And how do I fix this?

    Thanks.

    PS: V_gate = ~3.4V
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    My first guess is that C1-C2 combination making a filter with R1 and R3, which phase-shifts the gate voltage enough to start oscillation. Why do you have those caps there?
     
  3. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
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    That's what I first thought too, but removing them don't help much, it still oscillate at ~143KHz, ~250mV ripple when the V_drain = 5V.

    When V_drain = 6V, it oscillate at ~167KHz, ~35mV ripple, when V_drain > 7V, the oscillation seen to stop.
     
  4. kubeek

    AAC Fanatic!

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    Do you have decoulpling caps on the supply of the opamp? Try lowering R1 to say 47ohms or something, and putting R3 between gate and source.
     
  5. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Try to add a 10K RF resistor between V(-) input and source of a MOSFET.
    Have you try to use a different type of a MOSFET?

    As kubeek mentioned lowering R1 also should help.
     
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  6. Ron H

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    Apr 14, 2005
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    Do it like this.
    You might have to change some of the values, depending on your MOSFET.
    I don't think IRFB4030 is manufactured by anyone? is that a typo, or can you provide a link?
     
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  7. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
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    Thanks Ron H, your solution works best, now come to the question, why? and how do you calculate the value you suggested.

    datasheet for IRLB4030, sorry, it's my typo.

    PS:
    I find that C3 = 1n, 10n or 100n works quite well too, is that a reason why you choose a small value cap?
     
  8. Ron H

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    I haven't tried to analyze it. I run AC simulations (be sure to set a DC voltage on the input) while stepping the values of each passive component, and the drain voltage, one at a time. Try to minimize peaking in the AC response. If you are pulsing or stepping the current, try to maximize the bandwidth at same time.
    It's a good idea to run transient response tests with a pulse input waveform also, just to see how pulse response corresponds to various AC response curves.
     
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  9. bug13

    Thread Starter Well-Known Member

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    I am not sure if I am totally understand what you are explaining, but that could be very likely something I need to know but I don't know yet.

    But I think I sort of know what I need to learn and what to look for next time, thanks a lot.
     
  10. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
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    Can you explain why should I avoiding peaking in AC response? Are you referring to the peaking in gain, or are you referring to the peaking in phase?

    And in those graph, how can I tell graph is which value?
     
  11. Ron H

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    Attached are Bode plots and transient response plots of the circuit. Note that I could not find a spice model of your transistor, so I chose one that should be similar.
    Note the frequency response peaking in the Bode plot (AC sweep) when Rg=100Ω. Note also that this corresponds to overshoot and ringing in the step response.
    The response is close to optimum when Rg=500Ω. With 1kΩ, it has more frequency response roll-off than is required for good stability and step response. If you are not applying fast edges to the control input, this would be fine.
    Try the simulation with C3=0. Note the huge peak in frequency response. This is indicative of instability, and the circuit will probably oscillate, especially if you leave Rg in the circuit (as you have already discovered). Adding capacitance from gate to ground just makes the problem worse, because it introduces even more phase shift around the loop.
    My circuit works by isolating the gate capacitance from the op amp output with Rg, then applying high frequency feedback through the capacitor, bypassing the excessive phase shift caused by Rg and the gate capacitance.
    If you run more simulations, you will find that practically anything you change will cause the response to change. If you add a load resistance in the drain circuit, or change the drain supply voltage, the response will change. You might want to play around with the simulation and try some of these things.
    I have included the .ASC file. You might have to create a model for LM358.
     
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  12. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
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    [​IMG]

    Hi Ron H

    Thanks again for explaining it to me, it really help a lot.

    While I am playing around with the simulation, the graph generates in LTSpice doesn't label which line is which, are you using LTSpice as well? Is there a setting somewhere that I can enable the label on the graph?

    Again, thanks a lot
     
  13. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    You can turn phase plots on and off by right-clicking on the right side vertical axis.
    When you are doing parameter stepping, resulting in multiple plots on the same screen, right-click on the waveform window, then left-click on Select Steps.

    The help file is pretty comprehensive. You might also find help here.
     
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