Odd DC simulation results using Hspice

Discussion in 'General Electronics Chat' started by Prawny, Jul 7, 2010.

  1. Prawny

    Thread Starter New Member

    Jul 7, 2010
    1
    0
    Hi,

    I am using Hspice to stimate the static power consumption of CMOS gates implemented using a 180nm tech from UMC. I designed a 4-input NOR gate with wn=240 nm, wp=1440 nm and minimum transistor lengths. Simulation after parasitic extraction shown that the design was correct. Later I designed a larger version of the gate (wn=1440nm and wp=6140nm and minimum transistor lengths).

    I expected the later gate to be faster and to have a larger static power consumption for every input vector (wider transistors imply a larger subthreshold conduction and larger reverse-bias leakage current).

    As expected, the larger gate resulted to be faster, but when all the inputs were set to 0 it had smaller static power consumption than the original (smaller) NOR gate.

    Can anybody explain this behavior?

    Thanks in advance.
     
  2. timrobbins

    Active Member

    Aug 29, 2009
    318
    16
    Can you just simulate a portion of the gate (a subset of transistors?) - with the aim of reducing to the smallest generic circuit quanta that may then allow you to compare your two sizing options in a simpler way - you could then vary parameters to gain a better understanding of how the static loss occuring.

    Ciao, Tim
     
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