nor Layout 1-error debug!

Discussion in 'Homework Help' started by perplexabot, Nov 12, 2013.

  1. perplexabot

    Thread Starter New Member

    Jul 3, 2012
    15
    0
    Hello all. I am currently trying to make a nor gate layout. I extracted the mos's from the schematic and made the connections. It passed DRC but failed LVS with only one mismatch. Any help will be much appreciated. I have attached the layout and the output file, I can attach the schematic too if need be (please let me know). Thank you for reading.

    [​IMG]
     
  2. WBahn

    Moderator

    Mar 31, 2012
    17,737
    4,789
    Not a lot to go on.

    It appears that the problem might be that you have a floating NWELL which is, perhaps, being extracted as a parasitic capacitor.

    Could you post the two netlists?

    BTW: Other than the floating NWELL, the layout looks correct, if I am correct in assuming what the various layers are, but it sure is a very poor layout and could be tightened up enormously. Remember, silicon real estate is very expensive.
     
  3. perplexabot

    Thread Starter New Member

    Jul 3, 2012
    15
    0
    Thank you for your reply. I am assuming by floating nwell, you mean the body of the middle pmos? In my schematic that is connected to the pmos' source. I didn't use analog environment, i used nc-verilog to simulate. I will try and extract the netlists now and edit this post with them. Sorry for my late reply.

    PS: I know this layout is poor : ( I have seen really fancy ones online, but I have no idea how to make "monolithic" transistors. Do i need to make my own transistors following DRC rules or could you somehow merge the two extracted pmos' from the layout? This is kind of off topic so sorry for that.
     
  4. perplexabot

    Thread Starter New Member

    Jul 3, 2012
    15
    0
    Here are the netlists:
    [​IMG]
    [​IMG]
     
  5. WBahn

    Moderator

    Mar 31, 2012
    17,737
    4,789
    Yes. Look at M3 of the extracted netlist. The bulk is connected to Node 2, which is floating. The source is Node 1.
     
    perplexabot likes this.
  6. perplexabot

    Thread Starter New Member

    Jul 3, 2012
    15
    0
    So how do I connect the nwell to the source? I assumed that since I had the metal1 path going from the drain of the top pmos to the source of the bottom one, the metal1 will be in contact with the bottom pmos' source?
     
  7. WBahn

    Moderator

    Mar 31, 2012
    17,737
    4,789
    I don't know the layout layers in your drawing, so I have to make some assumptions. You have the top NWELL abutting the area above it, which I am assuming is Vcc and has an N+ implant below it. That could be giving you the bulk tie.

    You normally put ohmic contacts into the wells and tie them to the source or, in logic layouts, to Vcc directly.
     
Loading...