Hi all,

I'm (trying) to teach myself some digital circuitry and I thought I'd give this forum a go for some understanding. Before you all get your knickers in a twist, I did search the forums and looked at the online textbook, I'm currently working from Floyd's, Digital Fundamentals. There's not much out on the Net that makes sense to me, I could may well be backward!

It's a fairly simple question. I'm trying to grasp the universality of NOR gates by doodling some circuits from Boolean expression that I scrounge up from where ever. I came across one that made me feel my understanding of Boolean Algebra was shaky:

X = (AB' + C')EG + (KF + HA)I'

I'm only interested in the following part at the moment:

AB'

Given:
2 input AND gate = AB
2 input NAND gate = (AB)'
2 input OR gate = A+B
2 input NOR gate = (A+B)'

AA = A
A'A' = A'

De Morgan's Theorem:
(A+B)' = A'B'
(AB)' = A'+B'

I drew this as the equivalent of an AND gate:

Then I drew this for AB', but my gut says something is wrong:

Is it correct?

Nomnom,
k00k1e

 

You are doing just fine and, yes, it is correct.

To check your work, you can either work the Boolean algebra backwards or apply DeMorgan's graphically (known as bubble logic) or even just draw the truth table and see if it matches what you started with.

And thank you, thank you, thank you for showing your work and explaining what you were trying to do and what you did clearly. That is becoming frustratingly rare, particularly in first posts. Thank you and welcome to AAC.

 

Hi again,

Working along at a very leisurely pace. I have a couple of more questions. First one, when can I cancel the bars? Are there any specific rules regarding this? From trying different things I've come to the conclusion that one can only cancel bars of equal length, are there any other cases?

Secondly, what I come up with first (with NOR gates), generally won't be correct in terms of inversions on the first pass, so I have to go back and re-draw. Obviously practice makes perfect, but is there a trick, or system, perhaps indicators that I can look out for to optimise? It feels like I'm missing something and spending too much time on each layer. Here's my circuit below for (AB'+C')EG:

Is it as optimised as it can be? I would say yes, but I've been known to get ahead of myself.

Nomnom,
k00k1e

PS. Please excuse the attractive mouse-writing.

 

Why are you trying to base things on "bars of equal length"? It sounds like you are focusing on mechanics and not concepts. The concept you need to be thinking of is the identity that

(A')' = A

Keep in mind that A can be anything, including a function of many variables. When written using overbar notation, the two bars will be exactly matched (i.e., same length over the same thing) and can be canceled.

You diagram looks fine. It's probably as simple as it gets if you are constrained to using 2-input NOR gates. Since you only give the final result and not your step-by-step procedure, there is really no way to comment on whether there is a better way to do it.