NOR Flash programming via FPGA(vhdl)

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rahdirs

Joined May 22, 2013
28
I completed simulating my NOR flash controller design with flash model file given by Vendor,

During simualtion,my sequence of operations is, first i'm doing a sector erase & then writing to 10 addresses & then i'm reading those addresses.
The data which i read back is all "FFFF"(which is data in flash after sector erase).So does this mean that my write sequence is wrong.


I did not post the next state process code of fsm
What could be wrong in this ?

------------------- Update ----------------------
I tested my code on hardware and it was working even though it was not working in the model.
So i removed my code from the post(which was there before this update),but why wouldn't it work in the model ?
 
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