Hi all,

I have a print (see attachment) which serves as a trig controller for a machine vision project. The purpose is to output a TTL high whenever S1 and D1 or S2 and D2 are overlapping. S1 and S2 are pulsetrains from a proximity sensor and D1/D2 are used to filter these pulses to output a trig when these overlapps. The issue we are having now is noise on the flip flop clock. The noise is extremely short and approx 2V. The consequence is: The output generates an output when theres noise on the clock -> a clear is neccessary before any valid signal could trig the output.
The obvious solution is to use a filter of some kind at the flip flop clock but this would also filter a valid pulse. Since the valid pulse is a result of a previous filtering (AND of S1/D1 or S2/D2) further filtering would cause problems. D1 and D2 are set by a software, hence the software know the filtering but as soon as we introduce another filtering the software is unaware of this.

I would prefere something like a schmitt trigger where the threshoild is adjustable. Is there anything like that or how would a solve this issue?

BR
Jongas

 

What bypass filtering do you have on your power regulator and the Vcc line? Does each IC have a .1 decoupling capacitor located very close to the power pin?

 

Try running shielded wire from clock directly to inputs. Bypass as much of the circuit board as possible with the cable run and try to tie it in directly next to the input pins. Shield is attached to ground at Osc end only.

Using a schimtt trigger buffer on the signal might also help, if the noise peaks are low enough that will remove them and square up the clock pulses too.