Newbie question on Testbench

Discussion in 'Embedded Systems and Microcontrollers' started by micktosin, Mar 6, 2014.

  1. micktosin

    Thread Starter New Member

    Mar 20, 2012
    19
    0
    Hello there, I programmed a code to divide my FPGA clock to my required frequency and then invert into two square wave, however I keep getting an error with the testbench stating "the module pulsegentb(file name) is instantiating itself".
    And also with the file reports stating "the instantiation depth of pulsegatetb/notgate/notgate....is 51. This might indicate a recursive instantiation, increasing limit to 75".
    Below is the code of the square wave generator and the test bench please can someone help me as to why I can't run the testbench?

    Test Bench
    ///////////////////////////////////////////////////////////////////////////////////////////////////


    module pulsegentb();
    wire igbtclk1, igbtclk2;
    reg clock, reset;

    always begin
    #1 clock =!clock;
    end

    initial begin
    clock = 0;
    reset = 0;

    #10
    $finish;
    end

    pulsegentb notgate(clock, igbtclock1, igbtclock2);

    endmodule

    Square wave generator
    ///////////////////////////////////////////////////////////////////////////////////////////////////
    module igbt_clock_gen (clock,reset,igbtclock1,igbtclock2);
    input clock,reset;
    output reg igbtclock1, igbtclock2;
    wire temp1;

    freq_div f1 (clock,reset,temp1);
    clock_multiplier c1 (temp1, igbtclock1,igbtclock2);
    endmodule

    module freq_div(clock,rst,clock_out);
    input clock,rst;
    output reg clock_out;
    reg [15:0] counter;

    always @(posedge clock or negedge rst)
    begin
    if(!rst)
    begin
    counter<=16'd0;
    clock_out <= 1'b0;
    end
    else
    if(counter==16'd6667)
    begin
    counter <= 16'd0;
    clock_out <= ~clock_out;
    end
    else
    begin
    counter<=counter+1;
    end
    end
    endmodule

    module clock_multiplier (clock, clock1, clock2);
    input clock;
    output clock1, clock2;

    assign clock1 = clock;
    assign clock2 = ~clock1;
    endmodule
     
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