I have attached a diagram of a trigger circuit whose output (C) triggers high only when the original clock transitions from low to high.

The two questions I need to answer are how the output would change when replacing the AND gate in the circuit with either an EXCLUSIVE-OR gate and a NOR gate.

I am having difficulty understanding the truth table the original produces?

Would the XOR gate trigger C high when either A or B transition from low to high?

Thanks in advance for any help

 

The circuit works based off of the time delay added from the inclusion of the NOT gate you have there... so, for a brief moment, before the delay of the NOT gate, both inputs are 1 on a 0 to 1 transition of the input.

To solve this for the others, simply replace the AND with the other gate and figure out what happens....

Edit: You should note that this is a timing diagram, not a truth table....

 

Thanks for your response.

I suppose that is what is confusing me. How can both inputs be 1 if the NOT gate is being introduced before the AND gate?

 

It's it due to the inverter's(NOT gate's) propagation delay. This is the time it takes for the output to reflect the input for a given function, in this case, inversion. That is to say that there is a small delay between getting a 1 on the input of an inverter and generating a 0 on the output, so a small portion of time there will be a 1 on the input and a 1 on the output!

See here and here.

 

Ok I believe i fully understand this now.

So when replacing with a XOR gate the instances that produce a 1 as output will be almost the entire time except when the propagation delay produces two 0's or 1's as input.

In regards to this circuit, this happens 4 times? (I have attached a diagram of what i think the output will produce with an XOR gate)

Now for when the NOR gate is implemented, the output will be 0 the entire time except for the third instance when the delay cause both A and B to produce a 0?

Thanks again.

 

Ok I believe i fully understand this now.

So when replacing with a XOR gate the instances that produce a 1 as output will be almost the entire time except when the propagation delay produces two 0's or 1's as input.

In regards to this circuit, this happens 4 times? (I have attached a diagram of what i think the output will produce with an XOR gate)

Now for when the NOR gate is implemented, the output will be 0 the entire time except for the third instance when the delay cause both A and B to produce a 0?

Thanks again.

The attached schematic is an AND gate still, though you told me that this was an XOR gate, your diagrams should be self-sufficient, meaning someone could look at your diagram and know you are trying to convey....

Other than that, your logic seems sound.

As an added bonus, you have created a positive edge detector using the AND gate, a negative edge detector with the NOR(active-low), and an edge detector(both rising and falling edges) with the XOR gate.
Though, this is usually too fast to really be useful...

 

The attached schematic is an AND gate still, though you told me that this was an XOR gate, your diagrams should be self-sufficient, meaning someone could look at your diagram and know you are trying to convey....

I apologize, I did not change the actual gates appearance only the output of C.

 

I apologize, I did not change the actual gates appearance only the output of C.

I know. I'm just saying that you should always strive to convey exactly what you are doing in a diagram. If someone just clicked on your image, they wouldn't know what you were doing. I had to continually tell myself that this is supposed to be a XOR timing diagram.