An example: Cascading positive and negative clocked FFs would allow the data to flow twice as fast. The first FF clocks on the positive edge, allowing the second FF to clock on the negative edge from the first FF data, allowing the two FFs to respond in one clock period. If both FFs operated from the same edge, then the second would have to wait one clock period to respond to the data from the first, taking two clock pulses total instead of one.

 

Dear Watsongrey or whoever it may be, Positive logic is for people with a positive outlook and negative logic is for people suffering from depression!
Example: "to be or not to be" from Hamlet is an example of logic oscillation.

What oscillation?

(2B) + (2B)' = T

 

A circuit can be designed using either positive going logic or negative going logic , you can design the same circuit using only positive logic through the whole circuit or you can design the circuit using only negative logic. Why would a designer choose negative gong logic over positive going logic or vise versa?

Positive going logic circuits is when the logic signals are low state and needs to be switch to a high state
Negative going logic circuits is when the logic signals are high state and need to be switched to a low state

A designer chooses the polarity of the logic circuit.

Some logic IC chips TTL or CMOS are negative edge triggered, I'm not talking about this.

There is nothing that says that a given design has to be all positive-logic or all negative-logic. By mixing logic polarities within the same design, it is often possible to achieve greater gate optimization. It basically gives the designer more degrees of freedom to work with.

Also, the term positive "going" logic is misleading because the word "going" implies that there is a focus on a transition. It is this mislead that is causing all the confusion regarding whether you are talking about logic polarity or edge-trigger polarity. Positive logic is when a HI voltage is interpreted as a HI logic level, while negative logic is when a LO voltage is interpreted as a HI logic level.

 

and just cascading negative and positive going clocks would not work on everything. if a signal is hi for a short time or a long time would mean different clock transitions. if all the stages of a counter need to change state at the same time (synchronous counter) then you clock all at the same time, and transfer when the count is done. more like a register.that way all the transitions are at the same time.

 

What do you call a circuit that the logic is Positive, what i mean is that all the logic states default or start at logic low state and need to be tripped or triggered to a logic high, what would this be called? i was calling it "logic positive going"

When a circuit design logic polarity is Positive , the power and current draw is "more" compared to the same circuit design logic polarity is Negative? the Negative logic polarity draws less current and power? why is that

Edge Triggered Polarity is based on what inside the TTL or CMOS chip? what sets the edge trigger polarity inside the IC chip?

How does the Edge triggered polarity affect a circuits delay,clock periods or sync?

When would I use the word "going" is when a circuit is in transition? or the logic is alternating?

 

I don't know how common this is today, but it wasn't at all uncommon in days past for processors to take the input clock and produce two clocks at half speed that were in quadrature and then use both edges of those clocks to shepherd data through the logic so as to keep the data paths and control signals synchronized but separated.

 

for positive logic, a 7400 chip is a quad NAND gate, for negative logic, it is a quad NOR gate. same chip, just determined by how the logic is drawn. same real logic, two hi's in give a low out, for negative logic nor, any low in gives a high out.

 

What do you call a circuit that the logic is Positive, what i mean is that all the logic states default or start at logic low state and need to be tripped or triggered to a logic high, what would this be called? i was calling it "logic positive going"

The logic states default to whatever state the designer designs them to default to (which may be no default at all and they start up in whatever state they settle at during the start-up process). A design can easily have signals Fred and Bob default to LO and Sue and Tammy default to HI. Your question assumes a level of universality that simply doesn't exist.

When a circuit design logic polarity is Positive , the power and current draw is "more" compared to the same circuit design logic polarity is Negative? the Negative logic polarity draws less current and power? why is that

It has been mentioned several times already. Why don't you go read up on how TTL logic is actually implemented and you will see that inputs internally default to a high voltage level (which may or may not be a logic HI depending on what the designer of the circuit has chosen) and that they must be actively pulled to a low level by sinking current. Read a TTL data sheet to see the different current levels. CMOS is generally different and is much more symmetric -- and you do NOT leave CMOS inputs unconnected (it's not wise with TTL, but the behavior is generally pretty predictable).

Edge Triggered Polarity is based on what inside the TTL or CMOS chip? what sets the edge trigger polarity inside the IC chip?

The design of the circuit? This is like saying what makes a binary count in binary but a BCD counter count in BCD. The designer designed it to behave that way.

How does the Edge triggered polarity affect a circuits delay,clock periods or sync?

Poorly defined question. If I am using all positive edge triggered logic versus all negative edge triggered, then it has no effect as long as the detailed specs for the devices, such as setup and hold times and prop delays, do not depend on the trigger polarity (which they generally won't in general purpose families but might in internal standard cell libraries). If you are mixing the two in the same design, then how it affects the design depends on the specifics of the design -- it might make things better or might make things worse.

When would I use the word "going" is when a circuit is in transition? or the logic is alternating?

What do you mean "logic is alternating". The term "going" implies change. If you are "going to the store" it means that you are not at the store now but later you will be and that you are talking about that change of condition. So "positive going" means you are talking about something that is changing from something less positive to something more positive. It is entirely possible (and in fact there are communication protocols that do this) to define a logic HI as a positive-going transition of a signal and a logic LO as a negative-going transition (or vice-versa).

 

The logic states default to whatever state the designer designs them to default to (which may be no default at all and they start up in whatever state they settle at during the start-up process). A design can easily have signals Fred and Bob default to LO and Sue and Tammy default to HI. Your question assumes a level of universality that simply doesn't exist.

Yes by pull up or pull down resistors it will default to a logic state, or is there other ways of defaulting logic states?
Yes the designer designs them to default to either a Low state or High state. Why would a designer choose to default the logic state to a High state, so it needs to be tripped to a low state?
Because most Logic circuits are defaulted at a logic low state and needs to be switches to a logic High state
Other logic circuits i have seen are defaulted at a logic high state and needs to be switches to a logic low state
( I don't want to confuse the issue of polarity edge triggered chips being brought into this subject )

From what others have said is when a circuit design is defaulted at a High logic state and needs to be switches to a logic low state , has less current draw and power. Circuit designs that are defaulted to a low logic state and needs to be switched to a logic high state, draws more current and power.

If the circuit had no negative edge triggered chips , why would a designer default the logic signals to a logic high state so they need to be switched to a logic low logic state. The only reason is the current draw and power?

 

Your questions have been answered several times by several people and you keep just re-asking them and making the same baseless assumptions, such as "most logic circuit are defaulted at a logic low state and needs to be switches to a logic High state." Upon what basis do you make this claim? It has been pointed out several times that the current and power draw considerations apply to standard TTL logic and NOT to other logic families, but you keep ignoring that and claiming that it is universally the case. You keep bringing in nonsense about negative edge triggered chips when the polarity of the triggering has NOTHING to do with the polarity of the logic.

Since you refuse to learn from the answers people are giving you, why don't you go find some texts and read about it for yourself?

 

ok I must be missing something sorry