Some Logic circuits are negative going logic and others logic circuits are positive going logic signals.
What are the advantages of use either negative going or positive going logic?
Why would a designer choose to use a negative going logic then to use a positive going logic?

 

If you mean like as below:
negative going logic signal - 74LS74,74HC74
positive going logic signal - CD4013
negative and positive going logic signal - CD4518,74LS121,74HC121,74LS123,74HC123.

What kind of trigger logic you want to use, it depends on where is it place on.

 

Why would a designer choose to use a negative going logic then to use a positive going logic?

In 74xxx TTL, it takes less power to have active low logic i.e. mostly high until the signal is strobed. A logic low requires pulling current (a few ma for standard TTL, less for LSTTL) out of the input to make it low. Much less current is required to bias an input high so it makes sense to keep the quiescent levels high as much as possible, pulsing them low to count, latch etc. Also for TTL, the noise margin is better when this practice is followed. Grab a data sheet and compare the voltages for logic low and high. A logic low is closer to the grey zone (where the logic value is indeterminate) than a logic high - so if things are normally high, you have a bit more cushion. Most TTL devices (the ones I remember at least) mostly use normally high, strobing low inputs. Exceptions exist due to the requirements dictated by the logic function. The 7473 JK flip flop clock input comes to mind.

For 400x CMOS, things are more balanced between high and low (voltage-wise) and no appreciable current is required to drive an input either high OR low so the convention seems to have evolved to reflect the logic itself i.e. 1=TRUE.

 

Some Logic circuits are negative going logic and others logic circuits are positive going logic signals.
What are the advantages of use either negative going or positive going logic?
Why would a designer choose to use a negative going logic then to use a positive going logic?

Do you mean the direction of the edge trigger, such as for a FF, or do you mean whether a logic low or logic high is designated as a Logic 1?

 

He's back!!!

 

there is no real difference, when drawing logic, an inverter can be drawn either way, with the little circle denoting active low. counters and registers use the little circle to denote active low inputs and outputs. gates may be drawn either way, like a nand shown as a nor gate with active low inputs and an active high output. done for ease of reading the schematic. there is a little current difference between high and low, but open collector beats that.

 

He's back!!!

Curses! Are we talking about AKA Billy M?

 

I've had my suspicions

 

He's already been erased from EDABoard.

John

 

Curses! Are we talking about AKA Billy M?

Questions and writing style sure looks like him. These same questions are the ones that lead to the implosion at ETO.
But I get in trouble for this.

 

What does "the implosion at ETO" refer to? I'm getting a bunch of email spam from EDA Board which recently purchased ETO.

 

Dear Watsongrey or whoever it may be, Positive logic is for people with a positive outlook and negative logic is for people suffering from depression!
Example: "to be or not to be" from Hamlet is an example of logic oscillation.

 

A circuit can be designed using either positive going logic or negative going logic , you can design the same circuit using only positive logic through the whole circuit or you can design the circuit using only negative logic. Why would a designer choose negative gong logic over positive going logic or vise versa?

Positive going logic circuits is when the logic signals are low state and needs to be switch to a high state
Negative going logic circuits is when the logic signals are high state and need to be switched to a low state

A designer chooses the polarity of the logic circuit.

Some logic IC chips TTL or CMOS are negative edge triggered, I'm not talking about this.

 

Choosing logic polarity depends on what components are available at what price and cost effectiveness(least parts) that can perform the required function.

 

The Logic Polarity is true about some TTL and CMOS chips are negative edge triggered i can understand that.

How much current is a TTL logic low? or a CMOS logic low?
why is it a higher current for a Logic low state compared to a logic high state? because the internal transistors inside the Logic chips are turned on when it's in a logic low state , which draws more current and power?

 

Why are some TTL or CMOS chips negative edge triggered? what makes a logic chip negative edge triggered
Any reason why they would want a TTL or CMOS chip to be negative edge triggered instead of positive edge triggered?

 

because a counter clock input will clock on either a low going high, or a high going low, depending on how its designed. that way, they can keep thing sychronized. same for registers, the low going high is positive edge triggered and high going low is negative edge triggered. gates and inverters do not have triggers.

 

For a general pulse counter using a positive edge trigger, but for the timer need to using a negative edge trigger from second digits counter, otherwise the timer cann't get a precisely values.

 

But timers and counters are either positive or negative edge triggered
Yes i know that gates and inverters don't have trigger inputs.
They use the Negative edge trigger to get a delay or causes out of sync with other positive triggered edge signals
When you mix both positive and negative edge triggers view them on a multi-channel Logic analyzer they will not sync up to each other because the positive edge trigger Ic chips will get triggered before negative edge triggered IC chips which uses a delay or offset in time which causes things to go out of sync. When using a Logic analzyer and view mult-channel logic signals they should be in sync with each other. If they aren't in sync with each other or don't align up together then there is a positive edge and negative edge triggering problem unless the designer wants the Logic signals to go out of sync.

 

If you using two stages in series as CD4518 or 74LS90 and drawing their waveform then you will see the second digit timer should be used negative edge trigger.