Need help with circuit simulator

kubeek

Joined Sep 20, 2005
5,794
God, why would you want to do that?
Get Microcap or LTSpice or something, this java applet is nice to get some idea how things work, but certainly bad for getting the real results.
 

kubeek

Joined Sep 20, 2005
5,794
You didn´t say what the C pin does. Anyway, open the NOR schema in the simulator and go from there.
It´s in cirtuits - logic families - cmos - cmos nor
 

rapidcoder

Joined Jan 16, 2011
37
God, why would you want to do that?
Get Microcap or LTSpice or something, this java applet is nice to get some idea how things work, but certainly bad for getting the real results.
Oh'rly? I thought getting non-real results is a property of ALL circuit simulators. You get just some approximation. I've seen terribly inaccurate, useless traces from LTSpice and TINA, so judging Falstad's simulator only by its low model accuracy is not fair. Actually many engineers prefer more accurate and stable engine (like in NL5 for example) and simplified models, than the other way round. Getting slightly less accurate result is usually much better than getting no result at all, because of e.g. "timestep too small" problem, so common to all SPICE-based simulators.

A short comparison of Falstad's simulator and LTSpice:

Runs on ChromeOS: Falstad's - yes; LTSpice - no
Runs on *BSD, Solaris, Linux: Falstad's - yes; LTSpice - no
Time to install and run: Falstad's: no installation required; LTSpice - a few minutes, admin rights required
Interactive simulation: Falstad's - yes; LTSpice - no
Current flow visualization: Falstad's - yes; LTSpice - no
Crappy schematic editor GUI: Falstad's - yes; LTSpice - yes
Huge model library: Falstad's - no; LTSpice - mostly Linear Tech models only
Numerical instabilities and convergence problems: Falstad's - very common; LTSpice - common
Model accuracy: Falstad's - low; LTSpice - good; but that doesn't really matter that much because of problems mentioned in the previous point
 
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kubeek

Joined Sep 20, 2005
5,794
oh, now Im getting some idea what it should do..
Should it be edge or level triggered?
If you want it to be edge triggered, use the circuit here, the second picture from bottom. http://www.labri.fr/perso/strandh/Teaching/AMP/Common/Strandh-Tutorial/flip-flops.html I think the invertor on the left is not needed in a sr-latch.

If it should be just level triggered, ommit also the right half of the circuit, basically leaving just the and gates.
 
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