# Need help (Multiplexer/Comparator circuit)

Discussion in 'Homework Help' started by tbritti1, Aug 2, 2016.

1. ### tbritti1 Thread Starter New Member

Jul 23, 2016
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Hey everyone, I'm currently stuck on a lab that I have to complete for an online class I'm taking. I can't seem to wrap my head around it and my professor is incredibly hard to reach. I've attached a photo of my circuit on the breadboard, the procedure steps, and the incomplete schematic and truth table for the report.

My issue is that I don't understand how to determine the input of the multiplexer (D0-D7). I understand that my selector inputs will determine which input will pass through to the output, but how do I determine if my input should go to 0,1, B1, or B'1 as step 2 states. I'm also unsure of how to complete column X of the truth table. It seems like the output is determined by whether or not my jumper to the multiplexer inputs is going through the inverter or not.

I'm sure there's a simple explanation to this, but I need a little guidance in the right direction. Thanks.

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2. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
First of all you have to understand the operation of a parity generator. From the first two lines in the truth table, the output X needs to be a 1 if there are an even number of 1's in the input {0,2,4} and a 0 if there are an odd number of 1's in the input {1,3}. Does that help?

3. ### tbritti1 Thread Starter New Member

Jul 23, 2016
4
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Sorry, I forgot to mention that I'm not doing the further investigation questions. Those are the ones involving a multiplexer used as a parity generator.

4. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
If you cannot clearly describe the problem, then how do you expect us to give you a meaningful answer? Under the circumstances, what I can say is that, if you fill in the X column with an arbitrary pattern of 0's, 1's, B1's, and B1*'s then you can assign those values to the inputs {D0,...,D7} to produce that result. Once you do it the first time you won't even have to think about after that. You can do it by inspection. There 65,536 different ways of filling out the X column, and each of those can be realized by selecting one of the 4 possible values to each of the data inputs to the multiplexer.

5. ### tbritti1 Thread Starter New Member

Jul 23, 2016
4
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That's my problem. I'm trying to determine the results of the truth table but I can literally put whatever I want into the B1 input to give me any output that I want. This is all the information I was given to work with.

6. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
Doing a device that always outputs a 0 is easy. Doing a device that always outputs a 1 is also easy. Doing a device that outputs B1 is easy, as is doing a device that outputs the complement of B1. In order to fill in the X column you need to make a behavioral statement about the output. For example: "It is the associative AND of all four inputs". That is:

A1 & (A2 & (B1 & B2)))

So armed with that objective criteria, you fill in the table and apply the appropriate inputs. Now if you still cannot come up with an objective statement of how the output should behave, then I think you might want to consider devoting your energies elsewhere.

7. ### WBahn Moderator

Mar 31, 2012
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MOD NOTE: Moved to Homework Help.

8. ### RBR1317 Active Member

Nov 13, 2010
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There seems to be a conceptual problem there. The value of B1 is predetermined by the comparator input combinations A2,A1,B2,B1. The only value you need to be concerned with finding is the 'X' output in the truth table which will be equivalent to the output of the multiplexer. Also note that the truth table has 16 possible input combinations, but the multiplexer has only 8 data inputs. Before you do anything else, complete the truth table for a 2-bit comparator so you have the required value of the output 'X' for all 16 possible input combinations.

9. ### tbritti1 Thread Starter New Member

Jul 23, 2016
4
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OK, so I've got my outputs completed in the x column. In the example, they show the outputs as (1,0) and that connects to B'1 because they are complements. My next set of inputs is a (0,0), which I assume will go to logic 0, or ground. The next set of outputs is a (1,1). Does that mean that my multiplexer input D2 should connect to a logic 1?

10. ### RBR1317 Active Member

Nov 13, 2010
271
54
So now you have completed the truth table and it should look something like the following diagram. However, one should not refer to the outputs as a 'set' since each output condition is individual. Yet because of the 8:1 multiplexer design for 16 input conditions, they must be considered in pairs for the design of each multiplexer data input.

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