Hello,
I have uploaded a Mealy-Type FSM for a Serial Adder (it is from the book "Fundamentals of Digital Logic with VHDL Design by Stephen Brown and Zvonko Vranesic, second edition, page 515). I cannot understand why will FSM will remain in the same state for input valuations 01 and 10. For example, if the input valuation is 01 then the sum will be 1. Shouldn't it move to the next state? because if the sum is 1 there has to be a carry as well. Thanks in advance.
I have uploaded a Mealy-Type FSM for a Serial Adder (it is from the book "Fundamentals of Digital Logic with VHDL Design by Stephen Brown and Zvonko Vranesic, second edition, page 515). I cannot understand why will FSM will remain in the same state for input valuations 01 and 10. For example, if the input valuation is 01 then the sum will be 1. Shouldn't it move to the next state? because if the sum is 1 there has to be a carry as well. Thanks in advance.
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