Need help for simulating CMOS NAND logic gate using SPICE

Hello Everyone,
I'm in need for your help guys. I've to simulate a CMOS NAND logic gate using SPICE. I've written the code and run it via OrCAD PSPICE A/D.
I got the transient curve for V1,V3 and V4 but not sure those are correct. I'm confused. So, would like to get a review from experts here. Your kind help is desirable.And please I need the solution asap.

Thanks in Advance.
Oridroo

Here the code I written:

*NAND Gate with ref. parameter.
*spice option:
.width out=80
.options nopage nomode

*circuit description:
mpu1 2 1 4 4 penh w=33u l=3u
mpu2 2 3 4 4 penh w=33u l=3u

mnu1 4 1 4 0 nenh w=11u l=3u
mnu2 0 3 4 0 nenh w=11u l=3u
vdd 2 0 5

vin 1 0 pulse(0 5 0.3ns 0.3ns 0.3ns 20ns 40ns)
vin 3 0 pulse(0 5 0.3ns 0.3ns 0.3ns 40ns 80ns)
*model specifications

*NMOS model
.model nenh nmos level=2 vto=0.85
+kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 u0=624 uexp=0.055 vmax=20e4
+neff=9.8 delta=2.0
+cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33
+pb=0.81 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11

*PMOS Model
.model penh pmos level=2 vto=-0.85
+kp=12e-6 tox=470e-10 nsub=8.7e14
+ld=0.5e-6 u0=200 uexp=0.18 vmax=12e4
+neff=4.0 delta=2.0
+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33
+pb=0.7 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11

cout 4 0 50f

.tran 0.1ns 100ns
*.dc vin 0 5 0.1
.probe

.end

eta: Though I didn't got the solution from here, it's solved.