NAND RS Latch

Discussion in 'The Projects Forum' started by peter_morley, Aug 2, 2011.

  1. peter_morley

    Thread Starter Member

    Mar 12, 2011
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    I am confused about the initial state of a NAND RS latch when it is powered on. When S=R=1 the latch stays in the previous state it was in ie memory. If R is 0 and S is 1 the output is 0. If R is 1 and S is 0 the output is 1. Well according to that I would set both inputs to one at start up because it should be in the memory state. Why is the output 0 when it is in the memory state of both R and S = 1? Does this have to do with the timing of the circuit because I can't determine if the output should be 0 or 1. Every explanation just tells me this is the way it is and I have no idea why. Please help! Thanks, I attached a NAND RS latch picture.
     
  2. SgtWookie

    Expert

    Jul 17, 2007
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    If it's not initialized first, then its' state is undefined.

    One would usually add a small cap & resistor as an RC network to pull either the S or R line low during initialization to ensure that the beginning state is known.
     
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  3. peter_morley

    Thread Starter Member

    Mar 12, 2011
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    Great reply! I was thinking of adding a cap and resistor just to start the whole thing out.
     
  4. peter_morley

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    Mar 12, 2011
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    Ok now where do I put the cap and resistor in the circuit. I'm having trouble figuring out how I will pull it low and then have the circuit working fine after.
     
  5. SgtWookie

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    Like the attached.
     
  6. peter_morley

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    Mar 12, 2011
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    Thanks for the circuit! I used all of the components in your schematic including 4093 schmitt trigger NAND gates but I'm still getting Q and Qnot as logic level 1. And I believe when Q and Qnot are both 1 then the circuit is stuck and stops working. Any ideas as to what I'm doing wrong?
     
  7. SgtWookie

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    Jul 17, 2007
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    If the power-on voltage rise time is really slow, then 10nF might not be enough - or if your power switch is bouncing, that could also cause problems.

    One item I omitted is a discharge diode. Use something like a 1N4148/1N914 from the S input to Vdd, cathode towards Vdd. This discharges C1 quickly when the power goes off; otherwise the cap could hold a charge long enough to do damage to the 4093 input.
     
  8. peter_morley

    Thread Starter Member

    Mar 12, 2011
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    I increased capacitance with no luck. I then simulated a transient analysis on multisim and I also got a straight high logic for both q and qnot but what was also interesting is that the voltage does not increase from 0 to 5 in the RC circuit part. I'm probably missing something. Thanks for all the helpful stuff. I'm trying to create a shooting game with an IR transmitter/receiver and when I hit a target I need to keep the output high after hitting the object only once. Then I would change the state after a certain time. That is why I want to make this RS latch! I attached what I am getting for my transient analysis.
     
  9. SgtWookie

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    Jul 17, 2007
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    You need to have a ground connected to the negative terminal of V1. Right now, V1 has no ground reference.

    Note that the three nodes you've plotted are either at 1v or 1.25v instead of 0v or 4.9v to 5v.

    Also, I have used the "startup" parameter in LTSpice, which instructs the Spice simulator to start with all voltage sources at 0v. I don't know how to tell you the equivalent command/instruction/etc in Multisim, as I've never used it.
     
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  10. peter_morley

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    Mar 12, 2011
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    Oops made a newbie mistake again...haha I even noticed on my breadboard that one of my ground connections got disconnected by chance. I hooked the circuit up properly this time and wallaa it worked. Its funny how simple things can get so darn hard.
     
    Last edited: Aug 2, 2011
  11. SgtWookie

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    Jul 17, 2007
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    I'm glad you found the problem and got it working. :)
     
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