# NAND gate implementation

Discussion in 'Homework Help' started by TQ_07, Mar 7, 2007.

1. ### TQ_07 Thread Starter Member

Feb 22, 2007
11
0
i have the boolean expression:
AB + AC'D + A'B'CD'
and now have to design a NAND gate implementation of the circuit, this is what i have so far:
see attatched file​

can someone help me??

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2. ### Dave Retired Moderator

Nov 17, 2003
6,960
145
The same principles need to be applied as was the case in this question you asked previously, specifically using DeMorgan's theorum as expalined in this post of that thread.

You need to simplify your boolean expression so that is all in terms of NAND functions, at the moment you have OR-gates in there.

Dave

3. ### TQ_07 Thread Starter Member

Feb 22, 2007
11
0
the boolean expression i have was derived using a karnaugh map. in the karnaugh map i had three groups. which i then simplified to get this expression. i was told that i should have three terms in my simplified answer as i had three groups of terms, this can be seen in the karnaugh map

i have attatched my karnaugh map if you would like to look at it

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4. ### Dave Retired Moderator

Nov 17, 2003
6,960
145
For my understanding, can you clarify that when you say a NAND gate implementation you mean the resultant expression will be implemented using only NAND gates?

And you may wish to clarify what "three terms in my simplified answer" means.

Dave

5. ### TQ_07 Thread Starter Member

Feb 22, 2007
11
0
i have a group of four terms in my karnaugh map- that would be simplified to one term (AB) the group of two would be simplified to another term (AC'D) and then i have A'B'CD' on its own...so my answer would be:
AB + AC'D + A'B'CD'

i was told that this would be the simlified answer and could not be simplied any more

6. ### Dave Retired Moderator

Nov 17, 2003
6,960
145
Ok, before we dive in a deal with the Karnaugh Map can you answer the following two questions:

1. When you say a NAND gate implementation you mean the resultant expression will be implemented using only NAND gates?

2. You have been told by who that AB + AC'D + A'B'CD' is the simplified answer to the NAND gate implementation?

It is important that what I interpret as a NAND gate implementation is the same as what you interpret as a NAND gate implementation. Any clarification on these two questions is appreciated.

Dave