I have a N-Mos driven at 40Khz gated at 2Hz by a 555-based driver. It's driving a monitor flyback transformer using the low-side configuration. I worked the circuit for spans of 4 seconds. Power for the FET side is 70V PDC. the Gate voltage is 9v so both are well below what their datasheets put max values at.
Sadly, I burnt it.
There is no pull down resistor for the FET nor a resistor-diode snubber for the primary of the flyback. The FET has a sink and a fan nearby blowing at it.
Before you stomp at me for negleting these, I noted something.

I wired up everything religiously, but left the FET driver disconnected [so FET is OFF]. I found that a current of 0.7A flowed. No, the FET was good...I tested with another fresh one. Both had this happening.
I replaced the flyback with a normal 12v 0.3A computer power supply fan and the flow was absent. In theory, regardless of the presence of a worthy load or a short circuit, this flow should not happen...but in this case it is.
Why is this?

 

You cannot leave the gate not connected and expect the FET to be off.

 

If you leave the gate open, leakage currents will tend to charge up the gate and turn on the FET. I aways put a pull-down on the gate to avoid this.

 

If you leave the gate open, leakage currents will tend to charge up the gate and turn on the FET. I aways put a pull-down on the gate to avoid this.

Got it. The misbehavior has ceased.
Thanks gents.

 

I've removed this post because it's not viable with regards to this discussion. It might be misleading with this respect...
Sorry for any inonvenience.

 

If you leave the gate open, leakage currents will tend to charge up the gate and turn on the FET. I aways put a pull-down on the gate to avoid this.

Hi Jmac,
How to determine the best pulldown resistor value at the gate. Is the standard 4K7 okey?

 

So far the OP has not posted the part number of the FET.
Get the part number and read the data sheet.

 

Hi Jmac,
How to determine the best pulldown resistor value at the gate. Is the standard 4K7 okey?

I've found a 1K res to work for the IRFP450 NMOS, some chinese 'knockoffs' and a few others that I've scavenged from old dell M993 monitors.
Pretty much [500 Ω to 5 or 10K, the latter of which I found too high for the IRF, should work], this value should work for most if not all standard N-FETS.

 

So far the OP has not posted the part number of the FET.
Get the part number and read the data sheet.

I couldn't make out the part number correctly...it's fairly greased up with dust. Will try to post it tomorrow. Otherwise, the observations in the privious post hold alright.

 

Sizing the pull down resistor involves the gate capacitance of the Mosfet, the frequency you're using, and the driving voltage, maximum. It's about the time it takes to get back to "off" fast enough. That's why the part number is important, to find the gate capacitance.

 

fairchild FQPF 10N20 is the part number.
Frequency is 40Khz gated at 2Hz. Couldn't find intrinsic gate capacitance from its datasheet.
What's the equation?

 

Sizing the pull down resistor involves the gate capacitance of the Mosfet, the frequency you're using, and the driving voltage, maximum. It's about the time it takes to get back to "off" fast enough. That's why the part number is important, to find the gate capacitance.

That is assuming you use a single high side driver, so it can only charge the gate and the resistor is used to discharge it fast. But you should take the output maximum current into account too.

But if you drive the mosfet with any typical push-pull output like of the 555 or any microcontroller, then the driver takes care of both charging and discharging the gate capacitance. But still you should use a pull down resistor to keep the gate closed when the pin is floating, for example when the micro powers up all pins are configured as inputs.

 

I was thinking that the drive circuitry is very important, but I was feeling lazy today so I didn't provide a formula that might be useless without knowing what the driver is.

 

According to fairchild´s appnote http://www.fairchildsemi.com/an/AN/AN-7500.pdf the Ciss is the equivalent gate capacitance, ~600pF for this mosfet.

 

Nepdeep,
I usually use 100K, but almost anything will work.

 

@ Kubeek, I'm using low-side. I haven't yet got into building a working charge pump for highside... which I entend to use in another project. So at 600pF, what is the formulae to determine the pull-down resistor value?

 

@ Kubeek, I'm using low-side. I haven't yet got into building a working charge pump for highside... which I entend to use in another project. So at 600pF, what is the formulae to determine the pull-down resistor value?

I think there is some misunderstanding here, the mosfet is used as lowside switch, but the important thing is what drives the mosfet - if the output is open collector like the discharge pin in a 555 then you need to calculate the value - I would use whatever the max current allows, and then find the rc time constant of this and see if that is good enough.
If it is a complementary output like the output pin in a 555 which can both source and sink current, then just slap in there a 100k and be done with it, since it has almost no effect on the charge/dischrge timing.

 

I think there is some misunderstanding here, the mosfet is used as lowside switch, but the important thing is what drives the mosfet - if the output is open collector like the discharge pin in a 555 then you need to calculate the value - I would use whatever the max current allows, and then find the rc time constant of this and see if that is good enough.

my RC gating constant is 0.282sec [47uF and 6.1K] and the pulse RC constant is [6.3 x1 ^-6 sec]. max current I have measures, whilst pulsed is at -12A [whatever the -ve sign indicates...] at 80VPDC [consistent/average voltage].

If it is a complementary output like the output pin in a 555 which can both source and sink current, then just slap in there a 100k and be done with it, since it has almost no effect on the charge/dischrge timing.

I did with 1K and worked. I still however need to have that formulae to calculate this resistance value...just to know...
Thanks.

 

Basically the pulldown in the complementary case needs to be low enough so the leakage current of both the driver and the transistor D to G doesn´t create larger voltage than Vth. For example if you have leakage of 10uA and Vth of 2V then the resistor needs to be less than 200Kohm in order to prevent the transistor from turning on.

For gate capacitance of 1n you get discharge time of 200us after disconnecting the gate driver. I don´t really get what you mean by that first paragraph, maybe a schematic would be useful at this point.