Hi all,
I need a help with an implementation of fast 5to1 mux at transistor level. 4to1 in series with 2to1, 3to1 in series with another 3to1 etc. are not acceptable option since they are too slow. I also tried pass gates but parasitic gate-drain, gate-source capacities kill the rise/fall time completely. The select controls can be anything: binary, unary etc., the main idea is that it will be fast.
Thanks in advance.

 

Use part of an 8 to 1 MUX. What do you define as "fast"?

 

First of all I don't have 8to1 in my standard cells directory. Also, as far as I know, the implementation of 8to1 includes more than two pass-gates in series and thus is slow. As "fast" I define something like double pass gates (p-channel and n-channel) connected in parallel, but without its parasitic gate-drain capacity which comes strongly into account when the number of parallely connected pass gates is more than 3 (mux pass gate 3to1 ).
It must be smarter design.