multiple SPI buses on a single board

Discussion in 'General Electronics Chat' started by stroks, Jan 14, 2015.

  1. stroks

    Thread Starter New Member

    Aug 29, 2014
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    Hello everybody,

    Here is the problem:
    For my project I'm looking for a host adapter / micro controller that has several SPI buses. This is needed to control multiple long daisy chains of SPI devices.
    Hours of search yielded dozens of boards which all carry only a single SPI interface on-board. I wonder, are there any boards that have several (5 - optimal) SPI buses on a single board? It's not necessary that they have multiple slaves. They could also share the clock signal over this line. But absolutely necessarily that they have at least 5 MOSI lines.
    The host adapter solution could interface with a PC by USB or Ethernet or other ports. The ideal solution should have some Megabytes of memory on-board and an external trigger option.
    In case there is a micro-controller solution, it would be also nice to have some Mb of memory to store data and an external trigger, but I'm quite sure they all equipped with these.

    Looking forward for your ideas!
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    There are microcontrollers and devices with multiple SPI modules, though there comes a point of reduced return making other topologies and interfaces more suitable to the application.

    In other words, yes, there are devices that can have multiple SPI buses, but you probably won't find many that use them all.

    Perhaps you should explain why you'd want them so we can discuss alternatives.
     
  3. cmartinez

    AAC Fanatic!

    Jan 17, 2007
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    Two years ago I designed an 8051 based circuit that had 6 SPI independent lines. And what I did was programmed the protocol myself, which is called bit-banging. I suggest you try the same approach, it's laborious but not too difficult
     
  4. takao21203

    Distinguished Member

    Apr 28, 2012
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    no information about the speed is given.

    You can do software serial bus its just slower, and the slave has more overhead.

    If you have many slaves it might be better to have a buffering level, it could be you must wait for the slave since its using a primitive MCU which can only transfer in some time slot, or has a multiplexed IO.

    Some MCUs have addressable serial ports, if the address doesnt match it will just do nothing. You can also do that in software, use one signal to tell the slaves "now the address is sent".

    Or do you want more serial port lines for higher speed?
     
  5. stroks

    Thread Starter New Member

    Aug 29, 2014
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    Thanks for your reply.

    What do you mean with the point of reduced return?

    So the thing is that I have 50 switch chips, and 16 DAC chips. The switch chips gate the output of DACs to the proper output. Each of the chips has Clock signal, Data Input, Data Output and State Update pins. Thus, an SPI-like interface. DAC chips can be daisy-chained in a manner such that they share the common clock and state update (similar to CS) signals. The data to the whole chain is clocked through a single line that shifts data into the input of the first device into the chain and outputs data at its output which is connected to the next device in the chain.
    If all 16 DAC chips are connected into a single chain, the word to instruct all of them becomes extremely long. Because of this the speed of device operation becomes slow. But if I split this big chain into two independently instructed ones, the speed becomes sufficient. Same idea for the switch chips - they can be chained, but the instructing words become too long. In addition I would like to separate DAC and switch chips lines due to the different syntax of instructions they require.
    The data needs to clock into the chips devices at ~20 MHz rate. This is the upper limitation of their clock frequency. The speed can be less, but then the number of daisy chains should be increased to maintain the overall speed of operations.
    The amount of data that needs to be clocked is about 300-3000 kBits package every few seconds. For fast output it is preferable to store the data in the buffer of the board/controller and clock it out by receiving an external trigger signal.
     
  6. takao21203

    Distinguished Member

    Apr 28, 2012
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    the new PIC32MZ has Quad SPI.
     
  7. JWHassler

    Member

    Sep 25, 2013
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    Freescale has some ARMs with 6 SPI units. An FPGA implementation could have dozens. You have a lot a scope, here.
     
  8. tshuck

    Well-Known Member

    Oct 18, 2012
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    ... Meaning depending on the application, adding more SPI buses may not help.

    This approach seems reasonable, though. What are the "switch chip" details? They sound more like shift registers.
     
  9. stroks

    Thread Starter New Member

    Aug 29, 2014
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    0
    takao21203,
    Wow, PIC32MZ has even 6 of them! Something like this would be an ultimate solution. I'm quite new to electronics in general and not very familiar with terminology. So I wonder, how would you call a device which has this controller on-board with outlet terminals for all of the 6 SPIs and communication ports to program it from PC? Getting such a thing supplied with drivers for Visual C would save a lot of effort.

    JWHassler,
    So I looked up the processors Freescale has. And the optimal microcontroller chip they have is called MPC5748G. But now, if I want to use this chip's SPIs and program them with a PC via USB, where and what board types should I look for?

    tschuck,
    The switch chips are MAX14802. They are basically arrays of 16 switches with shift registers, where each of 16 bit controls the state of the corresponding switch.
     
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