MOSFET Switching Behaviour

Discussion in 'General Electronics Chat' started by jbriaris, Apr 18, 2013.

  1. jbriaris

    Thread Starter New Member

    Apr 11, 2013
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    Hi All

    I've been on a bit of a crash course learning about FETs, and, yes, I'm hoping for some more great pointers :).

    Consider the simple circuit shown in attached circ1.png, i.e., a N-channel logic-level MOSFET that switches the voltage being delivered to a voltage buffer. I am trying to understand more about the peaking shown in the voltage signal.

    With high values of R1 the peaking, or overshoot, becomes much more pronounced (Ids is also higher) than at lower levels of R1 (Ids lower). Am I right in thinking that R1 is 'working' with the capacitance of the MOSFET to create a pole in the system that causes this peaking, or is something else at play?

    How does one usually attempt to minimize this peaking? I have read about using small gate resistances on the MOSFET to slow the rise time, and also about impedance matching. Are these applicable in this situation?

    Thanx!!!! :)
     
  2. joeyd999

    AAC Fanatic!

    Jun 6, 2011
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    You are seeing what's called "charge injection". The rising/falling edge of the gate signal is being capacitively coupled to the drain, causing the peaks you are seeing.
     
  3. crutschow

    Expert

    Mar 14, 2008
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    The problem is you have used a MOSFET not appropriate to the application. To minimize the charge injection use a small CMOS IC switch instead of the large power MOSFET you show, which is designed to switch several amps of current and thus has a very large gate-drain capacitance.
     
  4. JMac3108

    Active Member

    Aug 16, 2010
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    The small gate resistors you read about are usually around 10 ohms. They are typically used for one of two purposes.

    (1) To slow down the edges of the switching waveform to reduce EMI. I've had to do this many times to get switching power supplies to pass FCC radiated emissions.

    (2) To prevent ringing or oscillation that occurs at the gate and distorts the switching waveform.
     
  5. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Also, you are driving the gate with zero rise and fall times. Start out with times that are appropriate for your real-world source. Also include the impedance of the source. Better yet, use a model of the source, if you have one.
    Once you have done this, you will get an idea of the real scope of the problem.
     
  6. jbriaris

    Thread Starter New Member

    Apr 11, 2013
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    Great, that set my head on the right path. Makes sense: the capacitive charge on the MOSFET discharges when the MOSFET is off, pushing more current into the circuit and causing the spiking.

    Reading a bit more from google it appears that the charge is injected into the source and drain, and is dependent on the switching speed.

    "There are lot many researches going on ,it is seen that if clock is very fast (turns off fast) the charge is equally distributed on both sides of the MOS. So we get 50% at C load side. If clock makes slow transition, all the charge could be absorbed at input." (REF-
    http://vlsi09manipal.blogspot.co.uk/2010/04/mosfet-can-be-used-as-switch-as-in.html )
    [​IMG]
    [​IMG]


    This makes perfect sense. However, the switching feeds into a constant current sink circuit that uses a n-channel mosfet to 'throttle' the current. So I guess I'll just end up seeing the same effect there anyway. Perhaps an npn transistor would be better to 'throttle' the current in the current sink circuit (less capacitance)? :confused:

    I would like to drive this from an MCU/SoC, so probably PWM to control the switching. Never done it before, but I guess the rise/fall times for PWM on such devices is pretty quick 5-20nS?
     
  7. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Look it up in the datasheet of the driving chip.
    Keep in mind that you will need a logic level MOSFET, i.e., one whose Rds(on) is specified when Vgs is less than or equal to the vcc of your driving chip. Also, consider the output current capability of that device.
     
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