MOSFET selection and setup for modified sine wave generator

Discussion in 'The Projects Forum' started by Marcus2012, Feb 26, 2015.

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  1. Marcus2012

    Thread Starter Member

    Feb 22, 2015
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    Hi again everyone

    Thanks for all the help getting me this far. I just have a few questions before I can start building this (I hope) so if I can get some help please it would be great :)

    I have attached the diagram below and everything switches ok and the output is nice in simulation. I just wanted to checkout the MOSFET setup and selection if that's ok.

    Basically

    1) They are all N-channel MOSFETS is this ok and the correct way to set this up optimally.
    2) The MOSFET I have selected have a GSth of 3.5-5 V so the supply (mark x on the diagram) to the phototransistor component of the opto-isolator is too high or ok? The reason I ask is that the source voltage of MOSFET y and z (marked) won't be 0V.
    3) This is the first time I've used MOSFETS and this is an inverter for a 12V car battery (30-40A). The MOSFETs I've looked at have an IDs of over that and power dissipation of over 400W but they seem tiny with tiny legs. Can they really handle this?
    4) Finally, do I need the gate resistors?

    Like I said this did work in a slowed down sim but I don't trust it over someones experience so I'd appreciate any help.

    Thanks all :)


    Link to MOSFET datasheet http://www.irf.com/product-info/datasheets/data/irfp4668pbf.pdf

    Diagram

    [​IMG]

    Edit : Link to the previous topic -- Scott Wang.
    1. CMOS 7555 abstable output @ 800 KHz - trangular wave instead of square, slew rate problem?
     
    Last edited: Feb 26, 2015
  2. ScottWang

    Moderator

    Aug 23, 2012
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    1. It's ok.
    2. (a) It's ok, a normal Mosfet can be input +/- 20V, what is the ID number of photocouple?
    (b) What kind of input?
    I already increasing the current of led of photocouple.
    3. To choose the Rated voltage for 3 times to what you need is better, otherwise the first concerned is the low Rds.
    Below are some other low Rds.

    IRF4110PbF_Nch_100V120A_Vgs10V_4.5mΩ.pdf
    STH260N6F6-2_Nch_60V180A300W_2.4mΩ_Vgs10V.pdf
    FDP8440_Nch_40V80A306W_Vgs4.5V_2.4mΩ.pdf

    You can calculate the power(watts) by yourself.

    4. The gate input connected to the same type of gate output is ok, there is no need to add the pull up resistor.

    5. I did some modified, Please check the a,b,c,d,e,f in the red circles.

    a - Adding D4 to inceasing the voltage.
    b - C6, C7 change from in series to in parallel.
    c - Adding C8(220uf/16V) to provide the load a more stable current.
    d - R3~R6, reducing the values of resistor, to make Q1~Q4 to get more base current.
    e - R7~R10, reducing the values of resistor, to make leds get more current.
    f - Took 4 Rg(2K) away, no needed, if you want then you can using 100Ω.

    Untitled_zpsfqg6elec_Marcus2012_02.png
     
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  3. Marcus2012

    Thread Starter Member

    Feb 22, 2015
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    Hey, thank you very much for that detailed reply, I have amended my diagram with your suggestions and I'm looking and opto-isolators at the moment but there was another few things that concern me. From what I understand about MOSFETs (which isn't much) particularly N-channel MOSFETs is a positive gate-to-source potential is necessary to create a conductive channel. I am having a little trouble understanding how I can create that in this application with an N-channel Mosfet without large losses. In the simulation the voltage at drain was 10V and gate 8V and at source about 6-7V (not accurate figures) . I did create an diagram using P-channel MOSFETs for transistors Q12 + 13 which is below and I loose much less potential over the P-channel MOSFETs. The Questions I have though are.

    1) Which is the superior design based on efficiency of the potential that reaches the load.
    2) In this version are the pull up and pull down resistors on the Q12 + 13 ok?
    3) I can't find any P-channels that have as high a power dissipation rating as N-channels so can I compensate for this, maybe by multiple in parallel from same gate control?

    Thanks again :)

    [​IMG]
     
    Last edited: Feb 27, 2015
  4. ScottWang

    Moderator

    Aug 23, 2012
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    You can take those two 20K pull down resistors away, because you already used the photo-transistors of photocouplers to do the pull down.
    Comparing to the n type that the p type is more less to pick up, you could go to the online seller to check.
    AON6411_Pch_20V85A_4.5V_2.5mΩ.pdf

    I was used the basic photocoupler PC817 to calculate the values, if you change to some other parts then probably you need to adjust the values.
     
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  5. Marcus2012

    Thread Starter Member

    Feb 22, 2015
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    Thank you for all of this help

    Those opto-couplers seem perfect for this so I'll go for them and I think I will use P-channels in parallel for Q12 + 13 as it seems the most efficient design based on my circuit losses.

    Time to order some parts :)
     
  6. ScottWang

    Moderator

    Aug 23, 2012
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