MOSFET PSPICE Circuit Simulation

Discussion in 'Homework Help' started by dcwang3, Nov 27, 2009.

  1. dcwang3

    Thread Starter New Member

    Nov 27, 2009
    7
    0
    Hi, I am trying to do a spice simulation of a dynamic circuit using PMOS and NMOS. Basically there is an precharge PMOS in series with the N-BLOCK LOGIC consists of the equation /A+BC, which is two parallel NMOS with one of the leg of the parallel has two NMOS in series, then in series with the evaluation NMOS.

    I have a vpulse for the clk on the PMOS and the bottom evaluation NMOS. Then I am just testing to see if the output changes with VDD or GND voltages going to the gates of the N-BLOCK LOGIC NMOS gates.

    The simulation looks correct for the case where all the NMOS gate inputs are 0V (means turned off), so the output stays high during the precharge and evaluation stage. But when I try to do different combinations on the gate inputs, it gives me pretty much the same result.

    Any suggestions?
     
  2. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    Post your schematic, and the results of your simulations.

    .PNG format is preferred. Use Ctrl+PrtScreen or Alt+PrtScreen to capture the screen image.
    Paste the image into MS Paint, crop it where necessary, and save as a type .png on your computer.

    Use the "Go Advanced" button below the reply box, then click "Manage Attachments" button near the bottom of the next screen to find/upload your images.
     
  3. dcwang3

    Thread Starter New Member

    Nov 27, 2009
    7
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  4. SgtWookie

    Expert

    Jul 17, 2007
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    OK, your P-ch MOS (M5) is upside-down. They don't work that way.

    Rotate it 180° and mirror it.
     
  5. dcwang3

    Thread Starter New Member

    Nov 27, 2009
    7
    0
    thanks it works fine now
     
  6. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    Good deal. :)

    I had a bit of a time getting the "hang" of MOSFETs.

    It helps a whole bunch if you remember to keep the source terminal pointed in the direction indicated by what the channel is.

    If it's a P-channel, you know that the source terminal should be towards the more positive area of the schematic; if it's an N-channel, you know that the source terminal should be towards the more negative area of the schematic.

    A basic guideline for creating schematics is that more positive voltages are near the top, more negative towards the bottom.

    Another basic guideline is that inputs should be towards the left side of the schematic, and outputs towards the right side. Since the gate of a MOSFET is the control input, you should try to orient the MOSFET so that the gate is on the left.
     
  7. kdillinger

    Active Member

    Jul 26, 2009
    141
    3
    What I hate the most about MOSFETs is that there are so many schematic symbols of them relative to bipolars. What gets me to this day is 3 terminal vs. 4 terminal. I have to stop and think.
     
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