Hello guys,
I've a problem that I was trying to solve for a while. I'll attach the main problem and the attempts that I've done

http://dl.dropbox.com/u/49829206/Photo Jan 11, 3 36 21 PM.jpg

And here's my solution

http://dl.dropbox.com/u/49829206/Photo Jan 11, 3 36 41 PM.jpg

Is that right? I want also to know for a point H what is a voltage there. As I've read that the voltage across it is zero . But I think its getting a feedback voltage from the ouput
Thanks!!

 

There are some assumptions that need to be made about this circuit. The PFETs are diode-connected, meaning that they have I-V characteristics similar to diodes. When the NFETs below them are off, they will tend to pull high. But when the NFETs are on, there will be contention and whether the diode-connect FET or the FET that is turned hard on wins depends on the FET parameters. So we have to assume that the NFET will win.

With this assumption, we can get at the truth table by answering the following questions:

Q1) By just considering Node C, under what conditions can C be pulled LO? Answer in terms of the terminals that Node C is attached to and not beyond that.

Q2) Now looking at the devices connected to Node C, what conditions are required at their other terminals in order to create the conditions noted above?

Q3) Now expand out one more layer and consider the devices connected to the other terminals of the devices connected to Node C. At this point, you should have your answers.

 

There are some assumptions that need to be made about this circuit. The PFETs are diode-connected, meaning that they have I-V characteristics similar to diodes. When the NFETs below them are off, they will tend to pull high. But when the NFETs are on, there will be contention and whether the diode-connect FET or the FET that is turned hard on wins depends on the FET parameters. So we have to assume that the NFET will win.

With this assumption, we can get at the truth table by answering the following questions:

Q1) By just considering Node C, under what conditions can C be pulled LO? Answer in terms of the terminals that Node C is attached to and not beyond that.

Q2) Now looking at the devices connected to Node C, what conditions are required at their other terminals in order to create the conditions noted above?

Q3) Now expand out one more layer and consider the devices connected to the other terminals of the devices connected to Node C. At this point, you should have your answers.

Yes I got that. But what confusing me is both points M and N . How could they affect my calculations.

https://www.dropbox.com/s/fo9il8s9i3isvfz/Photo Jan 11, 6 28 27 PM.jpg

As you see in red. I've assumed A to be 0 and b to be also zero.

Both fets are off so, vdd will be applied across the 2 parallel transistors which means that they are both "on " and we have path from both of them to (A's and B's output feedback) . if there's no feedback . So I can simply determine that c will be equal to zero or will be pulled down to GND

Thanks alot!

 

Yes I got that.

Then please provide that information so that we can be sure that you got it correctly and so that we can be sure that we are on the same page.

But what confusing me is both points M and N . How could they affect my calculations.

https://www.dropbox.com/s/fo9il8s9i3isvfz/Photo Jan 11, 6 28 27 PM.jpg

As you see in red. I've assumed A to be 0 and b to be also zero.

Both fets are off so, vdd will be applied across the 2 parallel transistors which means that they are both "on " and we have path from both of them to (A's and B's output feedback) . if there's no feedback . So I can simply determine that c will be equal to zero or will be pulled down to GND

You are making the common mistake of thinking that a voltage ON a node is the same as the voltage ACROSS "something". You say that "vdd will be applied 'across' the 2 parallel transistors". What do you mean by "across". The term "across", in this context, means a voltage difference between two nodes. What two nodes is vdd appearing across? In trying to answer that, you will hopefully realize that vdd is NOT being applied ACROSS anything (not the way you are meaning it), but rather is being applied TO two separate nodes. The gates of those two transistors each have Vdd appearing between their gate and ground. But that bring up your conclusion of "which means that they are both 'on' ". Just applying a voltage between a MOSFET gate and ground is NOT sufficient to turn it on -- this is controlled by the voltage ACROSS the gate-source terminals.

Remember, a transistor circuit is fundamentally an analog circuit. We call it a digital circuit and talk about a 0 turning "on" an PFET" and a 1 turning "on" an NFET, but this is only useful if this analog circuit obeys certain rules. This circuit does not obey them and so a 1 does not necessarily turn on an NFET.

Go back and clearly answer the questions I asked, and you will see that the path you are getting confused on is a nonissue.

 

There are some assumptions that need to be made about this circuit. The PFETs are diode-connected, meaning that they have I-V characteristics similar to diodes. When the NFETs below them are off, they will tend to pull high. But when the NFETs are on, there will be contention and whether the diode-connect FET or the FET that is turned hard on wins depends on the FET parameters. So we have to assume that the NFET will win.

With this assumption, we can get at the truth table by answering the following questions:

Q1) By just considering Node C, under what conditions can C be pulled LO? Answer in terms of the terminals that Node C is attached to and not beyond that.

Q2) Now looking at the devices connected to Node C, what conditions are required at their other terminals in order to create the conditions noted above?

Q3) Now expand out one more layer and consider the devices connected to the other terminals of the devices connected to Node C. At this point, you should have your answers.

A1 if one of terminals is equal to one it will be pushed down

A2 if A or B is equal 0

I've read your second post. But I'm still struggling with the concept of connecting the source of one MOSFETs to the gate of the other. I'm sorry for disappointing you

 

What if there's no connection between two MOSFETs and their sources are simply connected to ground. That will be so easy to solve

 

That's what I got so far

A = 1 B=1 C=1

A = 0 B=1 C=0

A = 1 B=0 C=0

But I'm still struggling with the case of A &B to be both zeroes

 

A1 if one of terminals is equal to one it will be pushed down

A2 if A or B is equal 0

I've read your second post. But I'm still struggling with the concept of connecting the source of one MOSFETs to the gate of the other. I'm sorry for disappointing you

Q1 asked you only to look at the terminals that C is directly connected to. It is not directly connected to A or B. It is connected to three things -- a PFET and two NFETs. The answer is that Node C will be pulled LO if either of the terminals connected to NFETs goes LO.

The next question then asks what it takes for one of the NFETs connected to Node C to pull Node C LO. For that to happen, two things must happen -- the other S/D terminal of the NFET has to be LO and the G terminal must be HI.

So what is required to take the G terminal of one of the NFETs HI while, at the same time, take the S/D terminal (not connected to C) LO.