Mosfet driver - Bootstrap capacitrance

Discussion in 'General Electronics Chat' started by Skeebopstop, Jan 9, 2009.

  1. Skeebopstop

    Thread Starter Active Member

    Jan 9, 2009
    358
    3
    Hey all,

    I am sizing a bootstrap capacitor for a half bridge mosfet class D audio amp. I am considering all factors (gate charge, high side driver level shift quiscent current etc..).

    What I am uncertain of, is lets say I outputting a very low frequency but my switching (modulating) frequency is 400kHz. So for example, my high side will have to switch on and off 1000 times (400Hz output) before the signal modulates through the low side driver to recharge the bootstrap capacitor. Won't I have to account for the fact that each switching cycle, basically the gate charge will be lost (returned to the bootstrap cap source through the gate driver push pull stage) and thus my bootstrap must store up enough charge to allow for so much returned gate charge?

    Any references I have seen only account for the quiscent currents and the total gate charge etc.., then multiply by 15 for a safety factor. I keep coming back to having to multiply nearly 1000 times, as the gate charge is generally the dominating factor in the calculation.

    In a design I have seen 0.33uF did the trick for a 200W amplified channel. My calculations roughly matched this with a safety factor of only 15 but with 150+ it would be getting quite large to be charged up in nearly a microsecond.

    Any assistance in settling my uneasy mind would be great. I don't want my amp to be suctacular if I decide to play some bass heavy tunes.

    Cheerio!

    James
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    The nature of class D is very similar to PWM control of a motor. The FET's are switched on and off at a constant frequency, but the ratio of on to off time during each period changes with the demand of the load - or speaker drive.

    So the amount of gate charge per period is constant - extra heavy bass just means the FET stays on longer.
     
  3. Skeebopstop

    Thread Starter Active Member

    Jan 9, 2009
    358
    3
    Hey Beenthere,

    thanks for that, however that is already quite clear. I realize the carrier (switching) frequency is fixed, in my case 400 kHz. However the example I am trying to outline is perhaps better outlined with an image.

    http://en.wikipedia.org/wiki/File:PWM,_3-level.svg (V(t) being supply and B(t) output).

    As you can see in the image, as the carrier modulates the rise of the output signal in the first quarter, it has to perform 3 on/off switches of the upper FET, if considering half bridge configuration. That means the gate would have had to have been charged and discharged at least 3 times. In reality I could imagine this to, on instance, be much much more than 3.

    Am I correct in thinking that each time the top FET switches on and off before we transition into the lower FET region, see image, that that charge is basically lost (i.e. returned to bootstrap cap)?

    Cheers
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    The FET will be turned on and off at the same frequency in all cases. The duration of its conduction will change, but the rate at which charge is placed onto the gate and pulled off is invariant.

    I think your example is for driving motors. Take a look at the Wikipedia article on class D - http://en.wikipedia.org/wiki/Switching_amplifier.
     
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