# MOSFET Biasing, Microelectronic circuits, Sedra

Discussion in 'Homework Help' started by alexei_kom, May 7, 2011.

1. ### alexei_kom Thread Starter New Member

Nov 22, 2009
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0
Hello everybody,

I'm having trouble understanding the following example (from Microelectronic circuits, Sedra):

k'*(W/L)=1 [mA/V^2]
Vt=1V
Vdd=15V

This is the circuit (with established voltages and currents):

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That's what written in the TB:
"Observe that the DC voltage at the drain (+10V) allows for a positive signal swing of +5V (i.e., up to Vdd) and a negative signal swing of -4V [i.e., down to (Vg-Vt)]."

I can't figure out how the negative signal swing is -4v? Maybe I'm interpreting this citation wrongly?

I found that the negative signal swing is -1.9V.

Here is my solution:

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2. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
783
Yes there is something strange about the statement. Suppose the FET were able to fully saturate such that VDS =0V. The maximum possible saturation drain current flow would then be 15V/20k or 0.75mA. In that case VD could fall to a minimum of 7.5V. The maximum possible asymmetrical drain voltage swing would then be +5V to -2.5V [certainly not -4V].

Perhaps the author is "inadvertently" considering the case where the source resistance is fully AC bypassed (by a capacitor of suitable value). In that case it would certainly be possible for the drain to swing to the -4V level offset - from the static 10V DC value.

3. ### alexei_kom Thread Starter New Member

Nov 22, 2009
9
0
Thanks for the reply!

I don't think that bypass capacitor was ment here because it is first introduced in later section of this chapter...

4. ### miguel cool New Member

Mar 15, 2010
9
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t refears that VD +ΔVD = 10V+5V positive swing

and VD +ΔVD = 10V-5V negative swing

that refears to the variation with respect the DC VD